From 3d4f7f66fd849e1876fe611503a6599cfd85d212 Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Sat, 31 Aug 2019 21:42:31 -0600
Subject: [PATCH] Updated to run with python3

---
 .travis/script.sh                        | 32 ++++++++----------------
 openfpga_flow/scripts/run_fpga_task.conf |  2 +-
 run_test.sh                              | 14 +++++------
 3 files changed, 19 insertions(+), 29 deletions(-)

diff --git a/.travis/script.sh b/.travis/script.sh
index 02627958c..04c8d3fec 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -6,28 +6,18 @@ set -e
 $SPACER
 
 start_section "OpenFPGA.build" "${GREEN}Building..${NC}"
-if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
-  #make
-  mkdir build
-  cd build
-  cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off
-  make -j16
-  alias python3.5="python3"
-  ln -s /opt/local/bin/python3 /opt/local/bin/python3.5
-else
-# For linux, we enable full package compilation
-  #make
-  mkdir build
-  cd build
-  cmake --version
-  cmake .. -DCMAKE_BUILD_TYPE=debug
-  make -j16
-fi
-end_section "OpenFPGA.build"
 
+mkdir build
+cd build
+
+if [[ $TRAVIS_OS_NAME == 'osx' ]]; then
+  cmake .. -DCMAKE_BUILD_TYPE=debug -DENABLE_VPR_GRAPHICS=off
+else
+  cmake .. -DCMAKE_BUILD_TYPE=debug
+fi
+ make -j16
+end_section "OpenFPGA.build"
 $SPACER
 
 cd -
-# python3.5 ./openfpga_flow/scripts/run_fpga_task.py regression/regression_quick
-chmod 755 run_test.sh
-python3.5 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow
\ No newline at end of file
+python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow
\ No newline at end of file
diff --git a/openfpga_flow/scripts/run_fpga_task.conf b/openfpga_flow/scripts/run_fpga_task.conf
index de0dac668..a9c373c0f 100644
--- a/openfpga_flow/scripts/run_fpga_task.conf
+++ b/openfpga_flow/scripts/run_fpga_task.conf
@@ -1,5 +1,5 @@
 [GENERAL CONFIGURATION]
 task_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/tasks
 misc_dir=${PATH:OPENFPGA_PATH}/openfpga_flow/misc
-python_path=python3.5
+python_path=python3
 script_default=${PATH:OPENFPGA_PATH}/openfpga_flow/scripts/run_fpga_flow.py
diff --git a/run_test.sh b/run_test.sh
index 58eb6e869..027a1bea4 100644
--- a/run_test.sh
+++ b/run_test.sh
@@ -1,4 +1,4 @@
-# python3.5 openfpga_flow/scripts/run_fpga_flow.py \
+# python3 openfpga_flow/scripts/run_fpga_flow.py \
 # ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \
 # ./openfpga_flow/benchmarks/MCNC_Verilog/s298/s298.v \
 # --top_module s298 \
@@ -16,7 +16,7 @@
 # --vpr_fpga_verilog_print_autocheck_top_testbench
 
 # Test popular multi-mode architecture
-python3.5 openfpga_flow/scripts/run_fpga_flow.py \
+python3 openfpga_flow/scripts/run_fpga_flow.py \
 ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \
 ./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
 --fpga_flow vpr_blif \
@@ -45,7 +45,7 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \
 --end_flow_with_test
 
 # Test Standard cell MUX2
-python3.5 openfpga_flow/scripts/run_fpga_flow.py \
+python3 openfpga_flow/scripts/run_fpga_flow.py \
 ./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \
 ./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
 --fpga_flow vpr_blif \
@@ -73,8 +73,8 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \
 --vpr_fpga_x2p_compact_routing_hierarchy \
 --end_flow_with_test
 
-# Test local encoder feature 
-python3.5 openfpga_flow/scripts/run_fpga_flow.py \
+# Test local encoder feature
+python3 openfpga_flow/scripts/run_fpga_flow.py \
 ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml \
 ./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
 --fpga_flow vpr_blif \
@@ -101,8 +101,8 @@ python3.5 openfpga_flow/scripts/run_fpga_flow.py \
 --vpr_fpga_x2p_compact_routing_hierarchy \
 --end_flow_with_test
 
-# Test tileable routing feature 
-#python3.5 openfpga_flow/scripts/run_fpga_flow.py \
+# Test tileable routing feature
+#python3 openfpga_flow/scripts/run_fpga_flow.py \
 #./openfpga_flow/arch/template/k6_N10_sram_chain_HC_tileable_template.xml \
 #./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
 #--fpga_flow vpr_blif \