From 3d234d840b051322479e4b132238e121b65eb5d7 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Sep 2020 20:31:11 -0600 Subject: [PATCH] [Documentation] Update documentation for the edge triggered attribute --- docs/source/manual/arch_lang/circuit_library.rst | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/docs/source/manual/arch_lang/circuit_library.rst b/docs/source/manual/arch_lang/circuit_library.rst index 59e5f055f..9e8466c09 100644 --- a/docs/source/manual/arch_lang/circuit_library.rst +++ b/docs/source/manual/arch_lang/circuit_library.rst @@ -143,7 +143,8 @@ A circuit model may consist of a number of ports. The port list is mandatory in .. option:: + is_global="" is_set="" is_reset="" + is_edge_triggered="" is_config_enable=""/> Define the attributes for a port of a circuit model. @@ -190,6 +191,8 @@ A circuit model may consist of a number of ports. The port list is mandatory in - ``is_config_enable="true|false"`` Specify if this port controls a configuration-enable signal. Only valid when ``is_global`` is ``true``. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the ``config_enable`` ports are connected to global configuration-enable voltage stimuli in testbenches. + - ``is_edge_triggered="true|false"`` Specify if this port is edge sensitive, like the clock port of a D-type flip-flop. This attribute is used to create stimuli in testbenches when flip-flops are used as configurable memory in frame-based configuration protocol. + .. note:: ``is_set``, ``is_reset`` and ``is_config_enable`` are only valid when ``is_global`` is ``true``. .. note:: Different types of ``circuit_model`` have different XML syntax, with which users can highly customize their circuit topologies. See refer to examples of :ref:``circuit_model_example`` for more details.