From 086642d13474a2768a5ad312b2014a673be968d5 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Feb 2022 15:33:24 -0800 Subject: [PATCH 1/4] [FPGA-Verilog] Now preconfigured wrapper can handle config_enable signals correctly --- openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp index fba957963..7c6862380 100644 --- a/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp +++ b/openfpga/src/fpga_verilog/verilog_preconfig_top_module.cpp @@ -235,6 +235,10 @@ int print_verilog_preconfig_top_module_connect_global_ports(std::fstream &fp, } else { VTR_ASSERT_SAFE(std::string(PIN_CONSTRAINT_OPEN_NET) == constrained_net_name); std::vector default_values(module_global_pin.get_width(), fabric_global_ports.global_port_default_value(global_port_id)); + /* For configuration done signals, we should enable them in preconfigured wrapper */ + if (fabric_global_ports.global_port_is_config_enable(global_port_id)) { + default_values.resize(module_global_pin.get_width(), 1 - fabric_global_ports.global_port_default_value(global_port_id)); + } print_verilog_wire_constant_values(fp, module_global_pin, default_values); } } From 123bb70cb361ad4ce6dd761c571c2063cb14c672 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Feb 2022 15:53:58 -0800 Subject: [PATCH 2/4] [Doc] More explanantion on the use of config_enable attribute for circuit ports --- docs/source/manual/arch_lang/circuit_library.rst | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/docs/source/manual/arch_lang/circuit_library.rst b/docs/source/manual/arch_lang/circuit_library.rst index 726d29c56..4ec803f99 100644 --- a/docs/source/manual/arch_lang/circuit_library.rst +++ b/docs/source/manual/arch_lang/circuit_library.rst @@ -195,7 +195,17 @@ A circuit model may consist of a number of ports. The port list is mandatory in - ``is_reset="true|false"`` Specify if this port controls a reset signal. All the reset ports are connected to a global reset voltage stimuli in testbenches. - - ``is_config_enable="true|false"`` Specify if this port controls a configuration-enable signal. Only valid when ``is_global`` is ``true``. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the ``config_enable`` ports are connected to global configuration-enable voltage stimuli in testbenches. + - ``is_config_enable="true|false"`` Specify if this port controls a configuration-enable signal. Only valid when ``is_global`` is ``true``. This port is only enabled during FPGA configuration, and always disabled during FPGA operation. All the ``config_enable`` ports are connected to global configuration-enable voltage stimuli in testbenches. + + .. note:: This attribute is used by testbench generators (see :ref:`fpga_verilog_testbench`) + + - In full testbench, + + - There is a ``config_done`` signal, which stay at logic ``0`` during bitstream loading phase, and is pulled up to logic ``1`` during operating phase + - When ``default_value="0"``, the port will be wired to a ``config_done`` signal. + - When ``default_value="1"``, the port will be wired to an inverted ``config_done`` signal. + + - In preconfigured wrapper, the port will be set to the inversion of ``default_value``, as the preconfigured testbenches consider operating phase only. .. note:: ``is_set``, ``is_reset`` and ``is_config_enable`` are only valid when ``is_global`` is ``true``. From 245c7b1e4508e6c0197b26e5b5123a6e359be4e2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Feb 2022 16:02:00 -0800 Subject: [PATCH 3/4] [Test] Add a new test case to validate config enable signal in preconfigured testbenches --- .../config/task.conf | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_enable_scff/config/task.conf diff --git a/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_enable_scff/config/task.conf b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_enable_scff/config/task.conf new file mode 100644 index 000000000..6b55acd3e --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/preconfig_testbench/configuration_chain_config_enable_scff/config/task.conf @@ -0,0 +1,44 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=yosys_vpr + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_cfgscff_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v +bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/or2/or2.v +bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v + +[SYNTHESIS_PARAM] +bench_read_verilog_options_common = -nolatches +bench0_top = and2 +bench0_chan_width = 300 + +bench1_top = or2 +bench1_chan_width = 300 + +bench2_top = and2_latch +bench2_chan_width = 300 + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= From cf31879b2086f4659f2c7a6286cba533067b3ca2 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 23 Feb 2022 16:03:56 -0800 Subject: [PATCH 4/4] [Test] Deploy new test to basic regression tests --- openfpga_flow/regression_test_scripts/basic_reg_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index bab6c6256..69e8cf4fb 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -23,6 +23,7 @@ run-task basic_tests/full_testbench/fast_configuration_chain_use_set --debug --s run-task basic_tests/full_testbench/smart_fast_configuration_chain --debug --show_thread_logs run-task basic_tests/full_testbench/smart_fast_multi_region_configuration_chain --debug --show_thread_logs run-task basic_tests/preconfig_testbench/configuration_chain --debug --show_thread_logs +run-task basic_tests/preconfig_testbench/configuration_chain_config_enable_scff --debug --show_thread_logs run-task basic_tests/preconfig_testbench/configuration_chain_no_time_stamp --debug --show_thread_logs echo -e "Testing fram-based configuration protocol of a K4N4 FPGA";