merged tutorial to online documentation and reworked compilation guidelines

README.md

@@ -6,7 +6,7 @@
 The OpenFPGA framework is the **first open-source FPGA IP generator** supporting highly-customizable homogeneous FPGA architectures. OpenFPGA provides a full set of EDA support for customized FPGAs, including Verilog-to-bitstream generation and self-testing verification [testbenches/scripts](./testbenches/scripts) OpenFPGA opens the door to democratizing FPGA technology and EDA techniques, with agile prototyping approaches and constantly evolving EDA tools for chip designers and researchers.
 
 ## Compilation
-Dependencies and help using docker can be found at [**./tutorials/building.md**](./tutorials/building.md).
+Dependencies and help using docker can be found [**here**](./docs/source/tutorials/building.rst).
 
 **Compilation Steps:**
 ```bash

docs/source/index.rst

@@ -12,14 +12,10 @@ Welcome to OpenFPGA's documentation!
    motivation
 
 .. toctree::
+   :maxdepth: 2
    :caption: Getting Started
 
-   eda_flow
-
-   run_fpga_flow
-
-   run_fpga_task
-
+   tutorials/index
 
 .. toctree::
    :maxdepth: 2
@@ -33,12 +29,6 @@ Welcome to OpenFPGA's documentation!
 
    fpga_bitstream/index
 
-.. toctree::
-   :maxdepth: 2
-   :caption: User Guide
-
-   tutorials/index
-
 .. toctree::
    :maxdepth: 2
    :caption: Appendix
@@ -52,8 +42,6 @@ For more information on the Yosys see yosys_doc_ or yosys_github_
 
 For more information on the original FPGA architecture description language see xml_vtr_
 
-
-
 Indices and tables
 ==================
 

docs/source/motivation.rst

@@ -65,10 +65,4 @@ FPGA-SPICE aims at generating SPICE netlists and testbenches for the FPGA archit
 
 SPICE modeling for FPGA architectures requires detailed transistor-level modeling for all the circuit elements within the considered FPGA architecture. However, current VPR architectural description language :cite:`JLuu_FPGA_2011` does not offer enough transistor-level parameters to model the most common circuit modules, such as multiplexers and LUTs. Therefore, we develop an extension on the VPR architectural description language to model the transistor-level circuit designs.
 
-In this manual, we will introduce how to use FPGA-SPICE to conduct an accurate power analysis. First, we give an overview of the design flow of FPGA-SPICE-based tool suites. Then, we show the command-line options of FPGA-SPICE. Afterward, we introduce the extension of architectural language and the transistor-level design supports. Finally, we present how to simulate the generated SPICE netlists and testbenches. 
-
-In the appendix, we introduce the hierarchy of the generated SPICE netlists and testbenches, to help you customize the SPICE netlists. We also attach an example of an architecture XML file for your interest.
-
 The technical details can be found in our ICCD’15 paper :cite:`XTang_ICCD_2015` and TVLSI'19 paper :cite:`XTang_TVLSI_2019`.
-
-

docs/source/tutorials/compile.rst

@@ -0,0 +1,68 @@
+How to Compile
+==============
+
+General Compilation Guidelines
+------------------------------
+OpenFPGA uses CMake to generate the Makefile scripts
+In general, please follow the steps to compile
+
+::
+
+  git clone https://github.com/LNIS-Projects/OpenFPGA.git
+  cd OpenFPGA
+  mkdir build
+  cd build            
+  cmake ..  -DCMAKE_BUILD_TYPE=debug 
+  make                             
+
+.. note:: OpenFPGA requires gcc/g++ version >5
+
+.. note:: cmake3.12+ is recommended to compile OpenFPGA with GUI
+
+.. note:: recommand to use ``make -j`` to accelerate the compilation
+
+Quick Compilation Verification
+To quickly verify the tool is well compiled, user can run the following command from OpenFPGA root repository
+
+::
+
+  python3 openfpga_flow/scripts/run_fpga_task.py compilation_verification --debug --show_thread_logs
+
+Dependencies
+------------
+Full list of dependencies can be found at travis_setup_link_
+In particular, OpenFPGA requires specific versions for the following dependencies:
+
+:cmake:
+  version >3.12 for graphical interface
+
+:iverilog:
+  version 10.1+ is required to run Verilog-to-Verification flow
+
+.. _travis_setup_link: https://github.com/LNIS-Projects/OpenFPGA/blob/0cfb88a49f152aab0a06f309ff160f222bb51ed7/.travis.yml#L34
+
+Docker
+------
+If some of these dependencies are not installed on your machine, you can choose to use a Docker (the Docker tool needs to be installed).
+For the ease of the customer first experience, a Dockerfile is provided in the OpenFPGA folder. A container ready to use can be created with the following command
+
+::
+
+  docker run lnis/open_fpga:release
+
+.. note:: This command is for quick testing. If you want to conserve your work, you should certainly use other options, such as ``-v``.
+
+Otherwise, a container where you can build OpenFPGA yourself can be created with the following commands
+
+::
+
+  docker build . -t open_fpga
+  docker run -it --rm -v $PWD:/localfile/OpenFPGA -w="/localfile/OpenFPGA" open_fpga bash
+
+For more information about dock, see dock_download_link_
+
+.. _dock_download_link: https://www.docker.com/products/docker-desktop
+
+To build the tool, go in the OpenFPGA folder and follow the compilation steps
+
+.. note:: Using docker, you cannot use ``make -j``, errors will happen

docs/source/tutorials/eda_flow.rst

@@ -5,7 +5,7 @@ As illustrated in :numref:`fig_eda_flow`, FPGA-SPICE creates a modified VTR flow
 
 .. _fig_eda_flow:
 
-.. figure:: figures/eda_flow.png
+.. figure:: ./figures/eda_flow.png
    :scale: 50%
    :alt: map to buried treasure
 
@@ -14,44 +14,3 @@ As illustrated in :numref:`fig_eda_flow`, FPGA-SPICE creates a modified VTR flow
 FPGA-Verilog is the part of the flow in charge of the Verilog and the semi-custom design flow. In our case, we use Cadence Innovus. The goal is to get the full-FPGA layout to complete the analysis provided by FPGA-SPICE. By having the layout, we can get an area analysis on the one hand and have new information concerning the power analysis. For instance, having the layout allows the user to have new information on the circuit such as the parasitics. 
 
 FPGA-Bitstream is the part of the flow in charge of the functional verification of the produced FPGA. Testbenches are generated by FPGA-Verilog and are combined with the full FPGA fabric in Modelsim. A bitstream is generated at the same time as the testbenches. This bitstream configures the FPGA with the functionality given by the user to VPR at the beginning of the flow. First, we configure the FPGA with the bitstream, and then waveforms are sent onto the I/O pads to check the functionality.
-
-
-How to compile
-==============
-Guides can be found in the *compilation* directory in the main folder. We tested it for MacOS High Sierra 10.13.4, Ubuntu 18.04 and Red Hat 7.5. This list is not exhaustive as other distributions could work as well.
-
-As a general rule, the compilation follows these steps:
-
-1) You clone the repository with:
-git clone --recurse-submodules https://github.com/LNIS-Projects/OpenFPGA,git
-
-Two different approaches exist from then on: Either you need the full flow, or you just need the extended version of VPR.
-If you need the full flow:
-
-2) Go into the folder you just cloned and make the different submodules through a global Makefile:
-cd OpenFPGA 
-mkdir build (*if folder doesn't already exist*)
-cd build
-cmake ..
-make OR make -j (*if you have multiple cores, this will make the compilation way faster*) 
-
-If you only need vpr:
-cd OpenFPGA 
-mkdir build (if folder doesn't already exist)
-cd build
-cmake ..
-make vpr/make vpr -j
-
-3) Architectures, circuits and already written scripts exist to allow you to test the flow without having to provide any new information to the system. For this:
-cd vpr7_x2p
-cd vpr
-source ./go_fpga_verilog/spice.sh
-
-They are scripts linking to a testing architecture and a simple circuit.
-
-4) If you only need to see the new options implemented in vpr, do:
-./vpr
-
-This step will show you all the different options which were added on top of VPR to enable deeper analysis of FPGA architectures.
-
-The released package includes a version of VPR with FPGA-SPICE, Verilog and Bitstream support, Yosys and ACE2.

docs/source/tutorials/index.rst

@@ -1,10 +1,18 @@
 .. _tutorials:
-   Tutorials
+   Getting Started
  
 .. toctree::
    :maxdepth: 2
 
-   getting_started
+   compile
+
+   eda_flow
+
+   run_fpga_flow
+
+   run_fpga_task
+
+   
   
 
    

tutorials/building.md

@@ -1,54 +0,0 @@
-# How to build?
-
-## Dependencies
-OpenFPGA requires all the following dependencies:
-- autoconf
-- automake
-- bash
-- bison
-- build-essential
-- cmake (version 3.12 for graphical interface or at least 3.X)
-- ctags
-- curl
-- doxygen
-- flex
-- fontconfig
-- g++-8
-- gcc-8
-- g++-4.9
-- gcc-4.9
-- gdb
-- git
-- gperf
-- iverilog
-- libcairo2-dev
-- libevent-dev
-- libfontconfig1-dev
-- liblist-moreutils-perl
-- libncurses5-dev
-- libx11-dev
-- libxft-dev
-- libxml++2.6-dev
-- perl
-- python
-- texinfo
-- time
-- valgrind
-- zip
-- qt5-default
-
-## Docker
-If some of these dependencies are not installed on your machine, you can choose to use a Docker (the Docker tool needs to be installed). For the ease of the customer first experience, a Dockerfile is provided in the OpenFPGA folder. A container ready to use can be created with the following command:
-- docker run lnis/open_fpga:release <br />
-*Warning: This command is for quick testing. If you want to conserve your work, you should certainly use other options, such as "-v".*
-
-Otherwise, a container where you can build OpenFPGA yourself can be created with the following commands:
-- docker build . -t open_fpga
-- docker run -it --rm -v $PWD:/localfile/OpenFPGA -w="/localfile/OpenFPGA" open_fpga bash<br />
-[*docker download link*](https://www.docker.com/products/docker-desktop)
-
-## Building
-To build the tool, go in the OpenFPGA folder and do:
-- mkdir build && cd build
-- cmake .. -DCMAKE_BUILD_TYPE=debug
-- make (*WARNING using docker you cannot use "make -j", errors will happen*)

tutorials/fpga_flow/folder_organization.md

@@ -1,30 +0,0 @@
-# fpga_flow folder organization
-
-The fpga_flow folder is organized as follow:
-* **arch**: contains architectures description files
-* **benchmarks**: contains Verilog and blif benchmarks + lists
-* **configs**: contains configuration files to run fpga_flow.pl
-* **scripts**: contains all the scripts required to run the flow
-* **tech**: contains xml tech files for power estimation
-
-## arch
-In this folder are saved the architecture files. These files are Hardware description for the FPGA written in XML. This folder contains 3 sub-folders:
-- **fpga_spice**: contains existing architecture ready to use.
-- **template**: contains template architecture which contain keyword to replace
-- **generated**: empty at the beginning, will host rewritten template
-
-## benchmarks
-This folder contains benchmarks to implement in the FPGA. it's divided in 3 folders:
-- **Blif**: Contains .blif and .act file to use in OpenFPGA. Benchmarks are divided in folder with the same name as the top module
-- **Verilog**: Contains Verilog netlist of benchmarks to use in OpenFPGA. Each project is saved in a folder with the same name as the top module.
-- **List**: Contains files with a list of benchmarks to run in one flow. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md#benchmark-list)
-
-## configs
-This folder contains configuration files required by openFPGA flow. They specify path to tools and benchmarks as well as flow utilization mode. More details are available in [fpga_flow tutorial](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md#configuration-file)
-
-## scripts
-This folder contains scripts call by OpenFPGA flow. Some of them can be used out of the flow as **pro_blif.pl** and **rewrite_path_in_file.pl** which respectively rewrite a blif file with 3 members on a ".latch" module to let it have 5 and replace a keyword in a file.<br />
-Any script provide help if call without argument.
-
-## tech
-This folder contains XML files describing the technology used. These files are used during power analysis.

tutorials/fpga_flow/how2use.md

@@ -1,88 +0,0 @@
-# FPGA Flow
-This tutorial will help the user to understand how to use the OpenFPGA flow.<br />
-During this tutorial, we consider that the user starts in the OpenFPGA folder and we will use tips and information provided in [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md#tips-and-informations). Details on how the folder is organized are available [here](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/folder_organization.md).
-
-## Running fpga_flow.pl
-A script example can be found at OPENFPGAPATHKEYWORD/fpga_flow/tuto_fpga_flow.sh.
-
-### Experiment
-cd fpga_flow<br />
-./tuto_fpga_flow.sh<br />
-
-### Explanation
-The *fpga_flow.pl* script takes an architecture description file (.xml), generates its netlists and generates a bitstream to implement a benchmark on the FPGA fabric and verifis its correct implementation.<br />
-When you open the perl script, you can see that 2 scripts are called. The first one is **rewrite_path_in_file.pl** which allows us to make this tutorial generic by generating full path to the dependencies.<br />
-The second one is **fpga_flow.pl**. This script launches the OpenFPGA flow and can be used with many different [options](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/options.md).<br />
-There are 3 important things to observe here:
-- All the FPGA-Verilog options have been activated
-- fpga_flow.pl calls a configuration file through the "config_file" variable
-- fpga_flow.pl calls a list of benchmark to be implemented and tested through the "bench_txt" variable
-
-### Configuration File
-In this file, paths have to be defined as **absolute** paths as relative paths could lead to errors.<br />
-The file is organized in 3 parts: 
-* **dir_path**: provides all the tool and repository paths
-* **flow_conf**: provides information on how the flow runs
-* **csv_tags**: *to be completed*
-
-When empty, the file is as follow:
-
-[dir_path]<br />
-script_base = OPENFPGAPATHKEYWORD/fpga_flow/scripts<br />
-benchmark_dir = *<Path to the folder containing all sources of the design>*<br />
-yosys_path = OPENFPGAPATHKEYWORD/yosys<br />
-odin2_path = not_used<br />
-cirkit_path = not_used<br />
-abc_path = OPENFPGAPATHKEYWORD/abc<br />
-abc_mccl_path = OPENFPGAPATHKEYWORD/abc<br />
-abc_with_bb_support_path = OPENFPGAPATHKEYWORD/abc<br />
-mpack1_path = not_used<br />
-m2net_path = not_used<br />
-mpack2_path = not_used<br />
-vpr_path = OPENFPGAPATHKEYWORD/vpr7_x2p/vpr<br />
-rpt_dir = *<wherever you want logs to be saved>*<br />
-ace_path = OPENFPGAPATHKEYWORD/ace2<br />
-
-[flow_conf]<br />
-flow_type = yosys_vpr *to use verilog input*<br />
-vpr_arch = *<wherever the architecture file is saved>*<br />
-mpack1_abc_stdlib = DRLC7T_SiNWFET.genlib # Use relative path under ABC folder is OK<br />
-m2net_conf = not_used<br />
-mpack2_arch = not_used<br />
-power_tech_xml = *<wherever the xml tech file is saved>*<br />
-
-[csv_tags]<br />
-mpack1_tags = Global mapping efficiency:|efficiency:|occupancy wo buf:|efficiency wo buf:<br />
-mpack2_tags = BLE Number:|BLE Fill Rate: <br />
-vpr_tags = Netlist clb blocks:|Final critical path:|Total logic delay:|total net delay:|Total routing area:|Total used logic block area:|Total wirelength:|Packing took|Placement took|Routing took|Average net density:|Median net density:|Recommend no. of clock cycles:<br />
-vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc Structures|lut6|ff<br />
-
-*This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial/tuto.conf*
-
-### Benchmark List
-The benchmark folder contains 3 sub-folders:
-* **Blif**: contains .blif and .act of benchmarks
-* **List**: contains all benchmark list files
-* **Verilog**: contains Verilog designs
-
-Blif and Verilog folders are organized by folders using the name of the projects. **The folder, top module and top module file must share the same name.**<br />
-The benchmark list file can contain as many benchmarks as available in the same folder targetted by the "benchmark_dir" variable from the configuration file. It's written as:<br />
-top_module/*.v,<int_value>; where <int_value> is the number of channel/wire between each block.
-
-*This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt*
-
-
-## Modifying the Flow
-Once the dependencies are understood, the flow can be modified by changing the architecture file and the route channel width.
-
-### Experiment
-* cd OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial
-* replace the architecture "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto.conf
-* cd OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List
-* replace "200" with "300" in tuto_benchmark.txt
-* cd OPENFPGAPATHKEYWORD/fpga_flow
-* replace the architecture "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto_fpga_flow.sh
-* ./tuto_fpga_flow.sh
-
-### Explanations
-With this last experiment, the [**K6 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut6.pdf) was replaced by a [**K8 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut8.pdf), which means that an 8-input fracturable LUT (implemented by LUT6 and LUT4 with 2 shared inputs) is used. This architecture provides more modes for the CLB and the crossbar which is changed from a half-connected to a fully connected, implying bigger multiplexors between the CLB and LUT inputs. These requirements in term of interconnection will lead an increase in the routing channel width. Indeed, if the routing channel is too low, it could be impossible to route a benchmark or the FPGA output could be delayed.

tutorials/fpga_flow/options.md

@@ -1,75 +0,0 @@
-# OpenFPGA flow options
-
-Usage -> **fpga_flow *-options <value>* **<br />
-Mandatory options: <br />
-- -conf <file> : *specify the basic configuration files for fpga_flow*
-- -benchmark <file> : *the configuration file contains benchmark file names*
-- -rpt <file> : *CSV file consists of data*
-- -N <int> : *N-LUT/Matrix*
-
-## Other Options:
-### General
-- -matlab_rpt <data_name> : *.m file consists of data compatible to matlab scripts. Specify the data name to be appeared in the script*
-- -I <int> : *Number of inputs of a CLB, mandatory when mpack1 flow is chosen*
-- -K <int> : *K-LUT, mandatory when standard flow is chosen*
-- -M <int> : *M-Matrix, mandatory when mpack1 flow is chosen*
-- -power : *run power estimation oriented flow*
-- -black_box_ace: *run activity estimation with black box support. It increase the power.*
-- -remove_designs: *remove all the old results.*
-- -multi_thread <int>: *turn on the mutli-thread mode, specify the number of threads*
-- -multi_task <int>: *turn on the mutli-task mode*
-- -parse_results_only : *only parse the flow results and write CSV report.*
-- -debug : *debug mode*
-- -help : *print usage*
-- -end_flow_with_test: *Uses Icarus Verilog simulator to verified bencmark implementation*
-### ODIN II
-- -min_hard_adder_size: *min. size of hard adder in carry chain defined in Arch XML.(Default:1)*
-- -mem_size: *size of memory, mandatory when VTR/VTR_MCCL/VTR_MIG_MCCL flow is chosen*
-- -odin2_carry_chain_support: *turn on the carry_chain support only valid for VTR_MCCL/VTR_MIG_MCCL flow *
-### ABC
-- -abc_scl : *run ABC optimization for sequential circuits, mandatory when VTR flow is selected.*
-- -abc_verilog_rewrite : *run ABC to convert a blif netlist to a Verilog netlist.*
-### ACE
-- -ace_p <float> : *specify the default signal probablity of PIs in ACE2.*
-- -ace_d <float> : *specify the default signal density of PIs in ACE2.*
-### VPR - Original Version
-- -vpr_timing_pack_off : *turn off the timing-driven pack for vpr.*
-- -vpr_place_clb_pin_remap: *turn on place_clb_pin_remap in VPR.*
-- -vpr_max_router_iteration <int> : *specify the max router iteration in VPR.*
-- -vpr_route_breadthfirst : *use the breadth-first routing algorithm of VPR.*
-- -vpr_use_tileable_route_chan_width: *turn on the conversion to tileable_route_chan_width in VPR.*
-- -min_route_chan_width <float> : *turn on routing with <float>* min_route_chan_width.*
-- -fix_route_chan_width : *turn on routing with a fixed route_chan_width, defined in benchmark configuration file.*
-### VPR - FPGA-X2P Extension
-- -vpr_fpga_x2p_rename_illegal_port : *turn on renaming illegal ports option of VPR FPGA SPICE*
-- -vpr_fpga_x2p_signal_density_weight <float>: *specify the option signal_density_weight of VPR FPGA SPICE*
-- -vpr_fpga_x2p_sim_window_size <float>: *specify the option sim_window_size of VPR FPGA SPICE*
-- -vpr_fpga_x2p_compact_routing_hierarchy : *allow routing block modularization*
-### VPR - FPGA-SPICE Extension
-- -vpr_fpga_spice <task_file> : *turn on SPICE netlists print-out in VPR, specify a task file*
-- -vpr_fpga_spice_sim_mt_num <int>: *specify the option sim_mt_num of VPR FPGA SPICE*
-- -vpr_fpga_spice_print_component_tb : *print component-level testbenches in VPR FPGA SPICE*
-- -vpr_fpga_spice_print_grid_tb : *print Grid-level testbenches in VPR FPGA SPICE*
-- -vpr_fpga_spice_print_top_tb : *print full-chip testbench in VPR FPGA SPICE*
-- -vpr_fpga_spice_leakage_only : *turn on leakage_only mode in VPR FPGA SPICE*
-- -vpr_fpga_spice_parasitic_net_estimation_off : *turn off parasitic_net_estimation in VPR FPGA SPICE*
-- -vpr_fpga_spice_testbench_load_extraction_off : *turn off testbench_load_extraction in VPR FPGA SPICE*
-- -vpr_fpga_spice_simulator_path <string> : *Specify simulator path*
-### VPR - FPGA-Verilog Extension
-- -vpr_fpga_verilog : *turn on OpenFPGA Verilog Generator*
-- -vpr_fpga_verilog_dir <verilog_path>: *provides the path where generated verilog files will be written*
-- -vpr_fpga_verilog_include_timing : *turn on printing delay specification in Verilog files*
-- -vpr_fpga_verilog_include_signal_init : *turn on printing signal initialization in Verilog files*
-- -vpr_fpga_verilog_print_autocheck_top_testbench: *turn on printing autochecked top-level testbench for OpenFPGA Verilog Generator*
-- -vpr_fpga_verilog_formal_verification_top_netlist : *turn on printing formal top Verilog files*
-- -vpr_fpga_verilog_include_icarus_simulator : *Add syntax and definition required to use Icarus Verilog simulator*
-- -vpr_fpga_verilog_print_user_defined_template : *Generates a template of hierarchy modules and their port mapping*
-- -vpr_fpga_verilog_print_report_timing_tcl : *Generates tcl script useful for timing report generation*
-- -vpr_fpga_verilog_report_timing_rpt_path <path_to_generate_reports> : *Specify path for report timing*
-- -vpr_fpga_verilog_print_sdc_pnr : *Generates sdc file to constraint Hardware P&R*
-- -vpr_fpga_verilog_print_sdc_analysis : *Generates sdc file to do STA*
-- -vpr_fpga_verilog_print_top_tb : *turn on printing top-level testbench for OpenFPGA Verilog Generator*
-- -vpr_fpga_verilog_print_input_blif_tb : *turn on printing testbench for input blif file in OpenFPGA Verilog Generator*
-- -vpr_fpga_verilog_print_modelsim_autodeck <modelsim.ini_path>: *turn on printing modelsim simulation script*
-### VPR - FPGA-Bitstream Extension
-- -vpr_fpga_bitstream_generator: *turn on FPGA-SPICE bitstream generator*

tutorials/tutorial_index.md

@@ -1,20 +0,0 @@
-# Tutorial Introduction
-OpenFPGA is an IP Verilog Generator allowing reliable and fast testing of homogeneous FPGA architectures.<br />
-Its main goal is to easily and efficiently generated a complete customizable FPGA and uses a semi-custom design flow.<br /><br />
-In order to help you get in touch with the software, we provide few tutorials which are organized as follow:
-* [Building the tool and his dependencies](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md)
-* [Launching the flow and understand how it works](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/fpga_flow/how2use.md)
-* Architecture modification
-
-## Folder Organization
-OpenFPGA repository is organized as follow:
-* **abc**: open source synthesys tool
-* **ace2**: abc extension generating .act files
-* **ace2**: abc extension generating activity files (.act)
-* **vpr7_x2p**: sources of modified vpr
-* **yosys**: opensource synthesys tool
-* **fpga_flow**: scripts and dependencies to run the complete flow
-
-## Tips and Information
-Some keywords will be used during in the tutorials:
-* OPENFPGAPATHKEYWORD: refers to OpenFPGA folder full path