diff --git a/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act b/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act
new file mode 100755
index 000000000..19f52fdd9
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.act
@@ -0,0 +1,10 @@
+IN0 0.505000 0.204400
+IN1 0.491000 0.206000
+IN2 0.472000 0.204400
+clk 0.500000 2.000000
+OUT1 0.491000 0.206000
+OUT0 0.505000 0.204400
+OUT2 0.472000 0.204400
+n15 0.491000 0.101146
+n18 0.505000 0.103222
+n21 0.472000 0.096477
diff --git a/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif b/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif
new file mode 100755
index 000000000..bf85b04b3
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.blif
@@ -0,0 +1,16 @@
+# Benchmark "routing_test" written by ABC on Tue Apr 21 18:25:21 2020 
+.model routing_test 
+.inputs IN0 IN1 IN2 clk  
+.outputs OUT0 OUT1 OUT2  
+ 
+.latch n15 OUT1 re clk 2 
+.latch n18 OUT0 re clk 2 
+.latch n21 OUT2 re clk 2 
+ 
+.names IN1 n15 
+1 1 
+.names IN0 n18 
+1 1 
+.names IN2 n21 
+1 1 
+.end 
diff --git a/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v b/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v
new file mode 100644
index 000000000..1cacf4857
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/routing_test/routing_test.v
@@ -0,0 +1,19 @@
+
+module routing_test(IN0,IN1,IN2,OUT0,OUT1,OUT2,clk);
+
+input wire IN0,IN1,IN2,clk;
+
+output reg OUT0, OUT1, OUT2;
+
+always @(posedge clk)
+	begin
+
+		OUT0  <=  IN0;
+		OUT1  <=  IN1;
+		OUT2  <=  IN2;
+
+	end
+
+
+
+endmodule