diff --git a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
index e390112e7..b1a588eb1 100644
--- a/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
+++ b/openfpga/test_vpr_arch/k6_frac_N10_adder_chain_40nm.xml
@@ -159,7 +159,7 @@
   </tiles>
   <!-- ODIN II specific config ends -->
   <!-- Physical descriptions begin -->
-  <layout tileable="true">
+  <layout tileable="false">
     <!--auto_layout aspect_ratio="1.0"-->
     <fixed_layout name="2x2" width="3" height="4">
       <!--Perimeter of 'io' blocks with 'EMPTY' blocks at corners-->
diff --git a/vpr/src/tileable_rr_graph/rr_gsb.cpp b/vpr/src/tileable_rr_graph/rr_gsb.cpp
index 200711e35..2d5c08e8c 100644
--- a/vpr/src/tileable_rr_graph/rr_gsb.cpp
+++ b/vpr/src/tileable_rr_graph/rr_gsb.cpp
@@ -874,8 +874,9 @@ void RRGSB::sort_chan_node_in_edges(const RRGraph& rr_graph) {
     SideManager side_manager(side);
     chan_node_in_edges_[side].resize(chan_node_[side].get_chan_width());
     for (size_t track_id = 0; track_id < chan_node_[side].get_chan_width(); ++track_id) {
-      /* Only sort the output nodes */
-      if (OUT_PORT == chan_node_direction_[side][track_id]) { 
+      /* Only sort the output nodes and bypass passing wires */
+      if ( (OUT_PORT == chan_node_direction_[side][track_id])
+        && (false == is_sb_node_passing_wire(rr_graph, side_manager.get_side(), track_id)) ) {  
         sort_chan_node_in_edges(rr_graph, side_manager.get_side(), track_id); 
       }
     }