From 5c8ca81645c2db583ffa6a7f61e51dff1f4d1f2a Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Fri, 1 Nov 2019 23:06:33 -0600
Subject: [PATCH 01/12] Travis failure debug

---
 .travis/script.sh | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/.travis/script.sh b/.travis/script.sh
index bbd72cec4..804d7303e 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -19,19 +19,19 @@ end_section "OpenFPGA.build"
 start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
 cd -
 echo -e "Testing single-mode architectures";
-python3 openfpga_flow/scripts/run_fpga_task.py single_mode 
-#python3 openfpga_flow/scripts/run_fpga_task.py s298 
+python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug
+#python3 openfpga_flow/scripts/run_fpga_task.py s298
 
-echo -e "Testing multi-mode architectures";
-python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4
+# echo -e "Testing multi-mode architectures";
+# python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4
 
-echo -e "Testing compact routing techniques";
-python3 openfpga_flow/scripts/run_fpga_task.py compact_routing 
+# echo -e "Testing compact routing techniques";
+# python3 openfpga_flow/scripts/run_fpga_task.py compact_routing
 
-echo -e "Testing tileable architectures";
-python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing 
+# echo -e "Testing tileable architectures";
+# python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing
 
-echo -e "Testing Verilog generation with explicit port mapping ";
-python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog 
+# echo -e "Testing Verilog generation with explicit port mapping ";
+# python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog
 
 end_section "OpenFPGA.TaskTun"

From 94b60b971468d181798535d673acd6e46fd61e8f Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Fri, 1 Nov 2019 23:12:56 -0600
Subject: [PATCH 02/12] Travis Test: Run 2

---
 run_test.sh | 120 ++++++++++++++++++++++++++--------------------------
 1 file changed, 60 insertions(+), 60 deletions(-)

diff --git a/run_test.sh b/run_test.sh
index 027a1bea4..b234523eb 100644
--- a/run_test.sh
+++ b/run_test.sh
@@ -18,14 +18,13 @@
 # Test popular multi-mode architecture
 python3 openfpga_flow/scripts/run_fpga_flow.py \
 ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml \
-./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
+./openfpga_flow/benchmarks/test_modes/test_modes.blif \
 --fpga_flow vpr_blif \
 --top_module test_modes \
---activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
---base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
+--activity_file ./openfpga_flow/benchmarks/test_modes/test_modes.act \
+--base_verilog ./openfpga_flow/benchmarks/test_modes/test_modes.v \
 --power \
 --power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
-#--fix_route_chan_width 300 \
 --min_route_chan_width 1.3 \
 --vpr_fpga_verilog \
 --vpr_fpga_verilog_dir . \
@@ -42,64 +41,65 @@ python3 openfpga_flow/scripts/run_fpga_flow.py \
 --vpr_fpga_verilog_print_sdc_pnr \
 --vpr_fpga_verilog_print_sdc_analysis \
 --vpr_fpga_x2p_compact_routing_hierarchy \
---end_flow_with_test
+--end_flow_with_test \
+--vpr_fpga_verilog_print_modelsim_autodeck /uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini
 
-# Test Standard cell MUX2
-python3 openfpga_flow/scripts/run_fpga_flow.py \
-./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \
-./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
---fpga_flow vpr_blif \
---top_module test_modes \
---activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
---base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
---power \
---power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
-#--fix_route_chan_width 300 \
---min_route_chan_width 1.3 \
---vpr_fpga_verilog \
---vpr_fpga_verilog_dir . \
---vpr_fpga_x2p_rename_illegal_port \
---vpr_fpga_verilog_include_icarus_simulator \
---vpr_fpga_verilog_formal_verification_top_netlist \
---vpr_fpga_verilog_include_timing \
---vpr_fpga_verilog_include_signal_init \
---vpr_fpga_verilog_print_autocheck_top_testbench \
---debug \
---vpr_fpga_bitstream_generator \
---vpr_fpga_verilog_print_user_defined_template \
---vpr_fpga_verilog_print_report_timing_tcl \
---vpr_fpga_verilog_print_sdc_pnr \
---vpr_fpga_verilog_print_sdc_analysis \
---vpr_fpga_x2p_compact_routing_hierarchy \
---end_flow_with_test
+# # Test Standard cell MUX2
+# python3 openfpga_flow/scripts/run_fpga_flow.py \
+# ./openfpga_flow/arch/template/k8_N10_sram_chain_FC_template.xml \
+# ./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
+# --fpga_flow vpr_blif \
+# --top_module test_modes \
+# --activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
+# --base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
+# --power \
+# --power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
+# #--fix_route_chan_width 300 \
+# --min_route_chan_width 1.3 \
+# --vpr_fpga_verilog \
+# --vpr_fpga_verilog_dir . \
+# --vpr_fpga_x2p_rename_illegal_port \
+# --vpr_fpga_verilog_include_icarus_simulator \
+# --vpr_fpga_verilog_formal_verification_top_netlist \
+# --vpr_fpga_verilog_include_timing \
+# --vpr_fpga_verilog_include_signal_init \
+# --vpr_fpga_verilog_print_autocheck_top_testbench \
+# --debug \
+# --vpr_fpga_bitstream_generator \
+# --vpr_fpga_verilog_print_user_defined_template \
+# --vpr_fpga_verilog_print_report_timing_tcl \
+# --vpr_fpga_verilog_print_sdc_pnr \
+# --vpr_fpga_verilog_print_sdc_analysis \
+# --vpr_fpga_x2p_compact_routing_hierarchy \
+# --end_flow_with_test
 
-# Test local encoder feature
-python3 openfpga_flow/scripts/run_fpga_flow.py \
-./openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml \
-./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
---fpga_flow vpr_blif \
---top_module test_modes \
---activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
---base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
---power \
---power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
---fix_route_chan_width 300 \
---vpr_fpga_verilog \
---vpr_fpga_verilog_dir . \
---vpr_fpga_x2p_rename_illegal_port \
---vpr_fpga_verilog_include_icarus_simulator \
---vpr_fpga_verilog_formal_verification_top_netlist \
---vpr_fpga_verilog_include_timing \
---vpr_fpga_verilog_include_signal_init \
---vpr_fpga_verilog_print_autocheck_top_testbench \
---debug \
---vpr_fpga_bitstream_generator \
---vpr_fpga_verilog_print_user_defined_template \
---vpr_fpga_verilog_print_report_timing_tcl \
---vpr_fpga_verilog_print_sdc_pnr \
---vpr_fpga_verilog_print_sdc_analysis \
---vpr_fpga_x2p_compact_routing_hierarchy \
---end_flow_with_test
+# # Test local encoder feature
+# python3 openfpga_flow/scripts/run_fpga_flow.py \
+# ./openfpga_flow/arch/template/k6_N10_sram_chain_HC_local_encoder_template.xml \
+# ./openfpga_flow/benchmarks/Test_Modes/test_modes.blif \
+# --fpga_flow vpr_blif \
+# --top_module test_modes \
+# --activity_file ./openfpga_flow/benchmarks/Test_Modes/test_modes.act \
+# --base_verilog ./openfpga_flow/benchmarks/Test_Modes/test_modes.v \
+# --power \
+# --power_tech ./openfpga_flow/tech/PTM_45nm/45nm.xml \
+# --fix_route_chan_width 300 \
+# --vpr_fpga_verilog \
+# --vpr_fpga_verilog_dir . \
+# --vpr_fpga_x2p_rename_illegal_port \
+# --vpr_fpga_verilog_include_icarus_simulator \
+# --vpr_fpga_verilog_formal_verification_top_netlist \
+# --vpr_fpga_verilog_include_timing \
+# --vpr_fpga_verilog_include_signal_init \
+# --vpr_fpga_verilog_print_autocheck_top_testbench \
+# --debug \
+# --vpr_fpga_bitstream_generator \
+# --vpr_fpga_verilog_print_user_defined_template \
+# --vpr_fpga_verilog_print_report_timing_tcl \
+# --vpr_fpga_verilog_print_sdc_pnr \
+# --vpr_fpga_verilog_print_sdc_analysis \
+# --vpr_fpga_x2p_compact_routing_hierarchy \
+# --end_flow_with_test
 
 # Test tileable routing feature
 #python3 openfpga_flow/scripts/run_fpga_flow.py \

From f042c35edfc1bf241d51e6f9047e26796f8b6891 Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Fri, 1 Nov 2019 23:26:31 -0600
Subject: [PATCH 03/12] Travis Experiments Squashed

---
 .gitignore        |   3 +-
 .travis.yml       | 176 +++++++++++++++++++---------------------------
 .travis/script.sh |  18 ++---
 deploy_key.enc    | Bin 0 -> 3248 bytes
 4 files changed, 84 insertions(+), 113 deletions(-)
 create mode 100644 deploy_key.enc

diff --git a/.gitignore b/.gitignore
index fc6dbf3a5..dade84a47 100644
--- a/.gitignore
+++ b/.gitignore
@@ -44,4 +44,5 @@ fpga_flow/csv_rpts
 tmp/
 build/
 
-message.txt
\ No newline at end of file
+message.txt
+deploy_key
\ No newline at end of file
diff --git a/.travis.yml b/.travis.yml
index 9d68dc6f4..f269bbd50 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -1,116 +1,86 @@
 language: cpp
-
-# cache results
-
 cache:
   directories:
-    - $TRAVIS_BUILD_DIR/abc
-    - $TRAVIS_BUILD_DIR/yosys
-    - $TRAVIS_BUILD_DIR/ace2
-    - $TRAVIS_BUILD_DIR/libs
-    - $HOME/.ccache
-    - $HOME/deps
-
-# Currently sudo is not required, NO ENV is used
-
-# Supported Operating systems
-#os:
-#  - linux
-#  - osx
-# Create a matrix to branch the building environment
+  - "$TRAVIS_BUILD_DIR/abc"
+  - "$TRAVIS_BUILD_DIR/yosys"
+  - "$TRAVIS_BUILD_DIR/ace2"
+  - "$TRAVIS_BUILD_DIR/libs"
+  - "$HOME/.ccache"
+  - "$HOME/deps"
 matrix:
   include:
-    - os: linux
-    # Compiler is specified in ./travis/common.sh
-      sudo: false
-      dist: bionic
-      compiler: g++-8
-      addons:
-        apt:
-          sources:
-          - ubuntu-toolchain-r-test # For newer GCC
-          - george-edison55-precise-backports # For cmake
-          packages:
-          - autoconf
-          - automake
-          - bash
-          - bison
-          - build-essential
-          - cmake
-          - ctags
-          - curl
-          - doxygen
-          - flex
-          - fontconfig
-          - g++-8
-          - gcc-8
-          - gdb
-          - git
-          - gperf
-          - iverilog
-          - libcairo2-dev
-          - libevent-dev
-          - libfontconfig1-dev
-          - liblist-moreutils-perl
-          - libncurses5-dev
-          - libx11-dev
-          - libxft-dev
-          - libxml++2.6-dev
-          - perl
-          - python
-          - texinfo
-          - time
-          - valgrind
-          - zip
-          - qt5-default
-#    - os: osx
-#      osx_image: xcode10.2 # we target latest MacOS Mojave
-#      sudo: true
-#      compiler: gcc-4.9 # Use clang instead of gcc in MacOS
-#      addons:
-#        homebrew:
-#          packages:
-#          - bison
-#          - cmake
-#          - ctags
-#          - flex
-#          - fontconfig
-#          - git
-#          - gcc@6
-#          - gcc@4.9
-#          - gawk
-#          - icarus-verilog
-#          - libxml++
-#          - qt5
-
+  - os: linux
+    sudo: false
+    dist: bionic
+    compiler: g++-8
+    addons:
+      apt:
+        sources:
+        - sourceline: ppa:ubuntu-toolchain-r/test
+        packages:
+        - autoconf
+        - automake
+        - bash
+        - bison
+        - build-essential
+        - cmake
+        - ctags
+        - curl
+        - doxygen
+        - flex
+        - fontconfig
+        - g++-8
+        - gcc-8
+        - gdb
+        - git
+        - gperf
+        - iverilog
+        - libcairo2-dev
+        - libevent-dev
+        - libfontconfig1-dev
+        - liblist-moreutils-perl
+        - libncurses5-dev
+        - libx11-dev
+        - libxft-dev
+        - libxml++2.6-dev
+        - perl
+        - python
+        - texinfo
+        - time
+        - valgrind
+        - zip
+        - qt5-default
 before_install:
-  - source .travis/common.sh
-
+- openssl aes-256-cbc -K $encrypted_6f6cf68308be_key -iv $encrypted_6f6cf68308be_iv -in deploy_key.enc -out ./deploy_key -d
+- eval "$(ssh-agent -s)"
+- chmod 600 ./deploy_key
+- echo -e "Host $SERVER_IP_ADDRESS\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config
+- ssh-add ./deploy_key
+- ssh -o StrictHostKeyChecking=no -i ./deploy_key u1249762@lab1-1.eng.utah.edu pwd
+- echo $TRAVIS_JOB_ID >> build_id.txt
+- scp -o StrictHostKeyChecking=no -i ./deploy_key build_id.txt u1249762@lab1-1.eng.utah.edu:/var/tmp/travis_bc/build_id.txt
+- source .travis/common.sh
 install:
-  - DEPS_DIR="${HOME}/deps"
-  - mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR}
-  - |
-    if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then
-      CMAKE_URL="https://cmake.org/files/v3.12/cmake-3.12.4-Linux-x86_64.tar.gz"
-      mkdir -p cmake && travis_retry wget --no-clobber --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake
-      export PATH=${DEPS_DIR}/cmake/bin:${PATH}
-      echo ${PATH}
-    else
-      brew install cmake || brew upgrade cmake
-    fi
-  - cmake --version
-  - cd -
-  - source .travis/install.sh
-
+- DEPS_DIR="${HOME}/deps"
+- mkdir -p ${DEPS_DIR} && cd ${DEPS_DIR}
+- |
+  if [[ "${TRAVIS_OS_NAME}" == "linux" ]]; then
+    CMAKE_URL="https://cmake.org/files/v3.12/cmake-3.12.4-Linux-x86_64.tar.gz"
+    mkdir -p cmake && travis_retry wget --no-clobber --no-check-certificate --quiet -O - ${CMAKE_URL} | tar --strip-components=1 -xz -C cmake
+    export PATH=${DEPS_DIR}/cmake/bin:${PATH}
+    echo ${PATH}
+  else
+    brew install cmake || brew upgrade cmake
+  fi
+- cmake --version
+- cd -
+- source .travis/install.sh
 script:
-  - .travis/script.sh
-  #- .travis/regression.sh
-
+- ".travis/script.sh"
 after_failure:
-  - .travis/after_failure.sh
-
+- ".travis/after_failure.sh"
 after_success:
-  - .travis/after_success.sh
+- ".travis/after_success.sh"
 notifications:
   slack:
     secure: L8tzicFh+EKcK21GBA2m3rQ3jmnDdqiRXIZcb0iqYlhT0V5asYvCqwlpPDUDV1wmBXqPgRJBI/jitAJlKFWu74pLTVc6FscUIDYM7S0DJfHEcufLknZx88lMmmV0IsYLQe3/s89tWoudMf1bNBo/8YWzLDffqUQ7s/rTPD9SWLppb01X0Xm158oDlA0rWETs35nuNFgJxWcSyIyIvnRNE3dHjzmBETUR9mYDsUSYlcOI44FMD8rE6emicdkqdn1zVxScobrl4Dt2bPsMfKopgIKK1x+38AuaqQa7t5F5ICnF0WfxmQ6/TcRNwIij0fDu68w/fcU8SyV+Ex5aZBKYUU7PG7ELTOq+q1geDoTlbguvFSIT4EzqErc4hbJmcUn79BKLhdjshZtGihKatntJx2faXYNYGFjwmnPFRYpqsozydztgMjzv4prZ5yoh7jhoDiGj44QcpXlQ9otM17JdfqveowMLHBYzATsxIRG93irZfXG/E3S8FvXg8mYOIEn8UK7H6i8VWL3JHlw8RbpLdNLswZOUlpEaDAeTm5tvYcw7FGH2nlZ2e5aXLxN6dTovSSRztQHbWdJTGG0N+xldBXcCiChmok4nXGReIkMc+99nZjRsiCB0R16tCNb25/p7NAVkItfVe1qRTzdnhi1hdE7LPURK4kxoFRJ6sFVuYjw=
diff --git a/.travis/script.sh b/.travis/script.sh
index 804d7303e..9e17f36c3 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -19,19 +19,19 @@ end_section "OpenFPGA.build"
 start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
 cd -
 echo -e "Testing single-mode architectures";
-python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug
+python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
 #python3 openfpga_flow/scripts/run_fpga_task.py s298
 
-# echo -e "Testing multi-mode architectures";
-# python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4
+echo -e "Testing multi-mode architectures";
+python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4
 
-# echo -e "Testing compact routing techniques";
-# python3 openfpga_flow/scripts/run_fpga_task.py compact_routing
+echo -e "Testing compact routing techniques";
+python3 openfpga_flow/scripts/run_fpga_task.py compact_routing
 
-# echo -e "Testing tileable architectures";
-# python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing
+echo -e "Testing tileable architectures";
+python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing
 
-# echo -e "Testing Verilog generation with explicit port mapping ";
-# python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog
+echo -e "Testing Verilog generation with explicit port mapping ";
+python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog
 
 end_section "OpenFPGA.TaskTun"
diff --git a/deploy_key.enc b/deploy_key.enc
new file mode 100644
index 0000000000000000000000000000000000000000..a5015fb2dd796bf4c4ec17b11224c01e3dff7b3a
GIT binary patch
literal 3248
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z^zn5!R3pk&60OC`s%%G|eNcZmcKFMQ9D-&$NX#I$yKkw_vf%glAqT#K$<4p?LJaH`
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za(YL?Ev?T`0NT93g+aKT9$%H+EhmRH(6B3q>l9)RN6s1IyuD8badFvn<p73jdixd!
zo3vHZR0^(@+M`CJ<ejaLNyReNPp`h&9A?4K>CfVZzE7|lyg9W};fqw9Iq-8qZM5*X
z{`KOp3na|SUJdadhnvkWd}!~H`2+*pD=>xABjmKFQ;6wV#m;nO)E<1BQMxi1GX8w6
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literal 0
HcmV?d00001


From 3ef978acccae5bc77ded02ff89a1e471096be5f0 Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Sat, 2 Nov 2019 16:37:00 -0600
Subject: [PATCH 04/12] Updated Encrypt Key

---
 deploy_key.enc | Bin 3248 -> 3248 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/deploy_key.enc b/deploy_key.enc
index a5015fb2dd796bf4c4ec17b11224c01e3dff7b3a..df15a29c9ef280daaf64f18fa9d565277a8228a6 100644
GIT binary patch
literal 3248
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From d14be73825da01c5e107a6e68ad794c4cee91d2f Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Sat, 2 Nov 2019 17:51:30 -0600
Subject: [PATCH 05/12] Added backup option in travis failure

---
 .travis.yml              | 9 +++++----
 .travis/after_failure.sh | 3 +++
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index f269bbd50..17b66e798 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -54,11 +54,12 @@ before_install:
 - openssl aes-256-cbc -K $encrypted_6f6cf68308be_key -iv $encrypted_6f6cf68308be_iv -in deploy_key.enc -out ./deploy_key -d
 - eval "$(ssh-agent -s)"
 - chmod 600 ./deploy_key
-- echo -e "Host $SERVER_IP_ADDRESS\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config
-- ssh-add ./deploy_key
-- ssh -o StrictHostKeyChecking=no -i ./deploy_key u1249762@lab1-1.eng.utah.edu pwd
+- cp $TRAVIS_BUILD_DIR/deploy_key ~/.ssh/id_rsa
+- echo -e "Host github.com\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config
+- ssh u1249762@lab1-1.eng.utah.edu pwd
+- ssh u1249762@lab1-1.eng.utah.edu "mkdir /var/tmp/travis_bc/$TRAVIS_JOB_ID"
 - echo $TRAVIS_JOB_ID >> build_id.txt
-- scp -o StrictHostKeyChecking=no -i ./deploy_key build_id.txt u1249762@lab1-1.eng.utah.edu:/var/tmp/travis_bc/build_id.txt
+- scp build_id.txt u1249762@lab1-1.eng.utah.edu:/var/tmp/travis_bc/$TRAVIS_JOB_ID/
 - source .travis/common.sh
 install:
 - DEPS_DIR="${HOME}/deps"
diff --git a/.travis/after_failure.sh b/.travis/after_failure.sh
index 95f8bd80c..fbbbda957 100755
--- a/.travis/after_failure.sh
+++ b/.travis/after_failure.sh
@@ -9,4 +9,7 @@ travis_fold end after_failure.1
 
 start_section "failure.tail" "${RED}Failure output...${NC}"
 tail -n 1000 output.log
+echo "Failed uploading files to LNIS Server"
+scp -qCr $TRAVIS_BUILD_DIR/openfpga_flow/tasks/ u1249762@lab1-1.eng.utah.edu:/var/tmp/travis_bc/$TRAVIS_JOB_ID/
+scp output.log u1249762@lab1-1.eng.utah.edu:/var/tmp/travis_bc/$TRAVIS_JOB_ID/
 end_section "failure.tail"

From c80cbfe8c9464eb60a63134c9e5af1a1a3733325 Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Sat, 2 Nov 2019 17:55:36 -0600
Subject: [PATCH 06/12] Removed files after regression test

---
 .travis.yml       | 2 +-
 .travis/script.sh | 9 +++++++--
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index 17b66e798..d4f2d90ad 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -55,7 +55,7 @@ before_install:
 - eval "$(ssh-agent -s)"
 - chmod 600 ./deploy_key
 - cp $TRAVIS_BUILD_DIR/deploy_key ~/.ssh/id_rsa
-- echo -e "Host github.com\n\tStrictHostKeyChecking no\n" >> ~/.ssh/config
+- echo -e "Host *\n  StrictHostKeyChecking no\n" >> ~/.ssh/config
 - ssh u1249762@lab1-1.eng.utah.edu pwd
 - ssh u1249762@lab1-1.eng.utah.edu "mkdir /var/tmp/travis_bc/$TRAVIS_JOB_ID"
 - echo $TRAVIS_JOB_ID >> build_id.txt
diff --git a/.travis/script.sh b/.travis/script.sh
index 9e17f36c3..09187ef2a 100755
--- a/.travis/script.sh
+++ b/.travis/script.sh
@@ -19,19 +19,24 @@ end_section "OpenFPGA.build"
 start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
 cd -
 echo -e "Testing single-mode architectures";
-python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
+python3 openfpga_flow/scripts/run_fpga_task.py single_mode
+python3 openfpga_flow/scripts/run_fpga_task.py single_mode --remove_run_dir all
 #python3 openfpga_flow/scripts/run_fpga_task.py s298
 
 echo -e "Testing multi-mode architectures";
-python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4
+python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 2
+python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --remove_run_dir all
 
 echo -e "Testing compact routing techniques";
 python3 openfpga_flow/scripts/run_fpga_task.py compact_routing
+python3 openfpga_flow/scripts/run_fpga_task.py compact_routing --remove_run_dir all
 
 echo -e "Testing tileable architectures";
 python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing
+python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing --remove_run_dir all
 
 echo -e "Testing Verilog generation with explicit port mapping ";
 python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog
+python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog --remove_run_dir all
 
 end_section "OpenFPGA.TaskTun"

From 333d10c94ce103f511917b9bafc725c2880238d2 Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Fri, 15 Nov 2019 14:26:57 -0700
Subject: [PATCH 07/12] Added vpr_fpga_verilog_print_simulation_ini option

---
 openfpga_flow/scripts/run_fpga_flow.py | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py
index 06a52e6d7..04634071f 100644
--- a/openfpga_flow/scripts/run_fpga_flow.py
+++ b/openfpga_flow/scripts/run_fpga_flow.py
@@ -191,9 +191,8 @@ VeriPar.add_argument('--vpr_fpga_verilog_print_top_tb', action="store_true",
 VeriPar.add_argument('--vpr_fpga_verilog_print_input_blif_tb',
                      action="store_true", help="Print testbench" +
                      "for input blif file in Verilog Generator")
-VeriPar.add_argument('--vpr_fpga_verilog_print_modelsim_autodeck', type=str,
-                     help="Print modelsim " +
-                     "simulation script", metavar="<modelsim.ini_path>")
+VeriPar.add_argument('--vpr_fpga_verilog_print_simulation_ini', action="store_true",
+                     help="Create simulation INI file")
 VeriPar.add_argument('--vpr_fpga_verilog_explicit_mapping', action="store_true",
                      help="Explicit Mapping")
 
@@ -721,9 +720,8 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
             command += ["--fpga_verilog_include_signal_init"]
         if args.vpr_fpga_verilog_formal_verification_top_netlist:
             command += ["--fpga_verilog_print_formal_verification_top_netlist"]
-        if args.vpr_fpga_verilog_print_modelsim_autodeck:
-            command += ["--fpga_verilog_print_modelsim_autodeck",
-                        args.vpr_fpga_verilog_print_modelsim_autodeck]
+        if args.vpr_fpga_verilog_print_simulation_ini:
+            command += ["--fpga_verilog_print_simulation_ini"]
         if args.vpr_fpga_verilog_include_icarus_simulator:
             command += ["--fpga_verilog_include_icarus_simulator"]
         if args.vpr_fpga_verilog_print_report_timing_tcl:

From f05aede868b4f088f66944ae336f7b516f17f1ab Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Fri, 15 Nov 2019 23:23:15 -0700
Subject: [PATCH 08/12] Added task support for modelsim script

---
 openfpga_flow/misc/modelsim_proc.tcl  |  2 +-
 openfpga_flow/scripts/run_modelsim.py | 84 ++++++++++++++++++++++++---
 2 files changed, 76 insertions(+), 10 deletions(-)

diff --git a/openfpga_flow/misc/modelsim_proc.tcl b/openfpga_flow/misc/modelsim_proc.tcl
index cede56af4..69972b764 100644
--- a/openfpga_flow/misc/modelsim_proc.tcl
+++ b/openfpga_flow/misc/modelsim_proc.tcl
@@ -47,7 +47,7 @@ proc top_create_new_project {projectname verilog_files modelsim_path simtime uni
   #Start the simulation
   vsim $projectname.$top_tb -voptargs=+acc
   #Add the waves
-  add_waves top_tb
+  add_waves $top_tb
   #run the simulation
   runsim $simtime $unit
   #Fit the window view
diff --git a/openfpga_flow/scripts/run_modelsim.py b/openfpga_flow/scripts/run_modelsim.py
index 0ddbe118c..2f4ac5fc4 100644
--- a/openfpga_flow/scripts/run_modelsim.py
+++ b/openfpga_flow/scripts/run_modelsim.py
@@ -1,12 +1,12 @@
 from string import Template
 import sys
 import os
-import pprint
+import re
+import glob
 import argparse
 import subprocess
 import logging
-from pprint import pprint
-from configparser import ConfigParser
+from configparser import ConfigParser, ExtendedInterpolation
 
 # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 # Configure logging system
@@ -20,7 +20,8 @@ logger = logging.getLogger('Modelsim_run_log')
 # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 parser = argparse.ArgumentParser()
 parser.add_argument('files', nargs='+',
-                    help="Pass SimulationDeckInfo generated by OpenFPGA flow")
+                    help="Pass SimulationDeckInfo generated by OpenFPGA flow" +
+                    " or pass taskname <taskname> <run_number[optional]>")
 parser.add_argument('--modelsim_proc_tmpl', type=str,
                     help="Modelsim proc template file")
 parser.add_argument('--modelsim_runsim_tmpl', type=str,
@@ -36,9 +37,32 @@ parser.add_argument('--modelsim_ini', type=str,
                     help="Skip any confirmation")
 parser.add_argument('--skip_prompt', action='store_true',
                     help='Skip any confirmation')
+parser.add_argument('--ini_filename', type=str,
+                    default="simulation_deck_info.ini",
+                    help='default INI filename in in fun dir')
 args = parser.parse_args()
 
-# Consider default formality script template
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Read script configuration file
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+task_script_dir = os.path.dirname(os.path.abspath(__file__))
+script_env_vars = ({"PATH": {
+    "OPENFPGA_FLOW_PATH": task_script_dir,
+    "ARCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "arch"),
+    "BENCH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "benchmarks"),
+    "TECH_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "tech"),
+    "SPICENETLIST_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "SpiceNetlists"),
+    "VERILOG_PATH": os.path.join("${PATH:OPENFPGA_PATH}", "VerilogNetlists"),
+    "OPENFPGA_PATH": os.path.abspath(os.path.join(task_script_dir, os.pardir,
+                                                  os.pardir))}})
+config = ConfigParser(interpolation=ExtendedInterpolation())
+config.read_dict(script_env_vars)
+config.read_file(open(os.path.join(task_script_dir, 'run_fpga_task.conf')))
+gc = config["GENERAL CONFIGURATION"]
+
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+# Load default templates for modelsim
+# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 task_script_dir = os.path.dirname(os.path.abspath(__file__))
 if not args.modelsim_proc_tmpl:
     args.modelsim_proc_tmpl = os.path.join(task_script_dir, os.pardir,
@@ -52,7 +76,49 @@ args.modelsim_runsim_tmpl = os.path.abspath(args.modelsim_runsim_tmpl)
 
 
 def main():
-    for eachFile in args.files:
+    if os.path.isfile(args.files[0]):
+        run_modelsim(args.files)
+    else:
+        # Check if task directory exists and consistent
+        taskname = args.files[0]
+        task_run = "latest"
+        if len(args.files) > 1:
+            task_run = f"run{int(args.files[1]):03}"
+
+        temp_dir = os.path.join(gc["task_dir"], taskname)
+        if not os.path.isdir(temp_dir):
+            clean_up_and_exit("Task directory [%s] not found" % temp_dir)
+        temp_dir = os.path.join(gc["task_dir"], taskname, task_run)
+        if not os.path.isdir(temp_dir):
+            clean_up_and_exit("Task run directory [%s] not found" % temp_dir)
+
+        logfile = os.path.join(gc["task_dir"], taskname, task_run, "*.log")
+        logfiles = glob.glob(logfile)
+        if not len(logfiles):
+            clean_up_and_exit("No successful run found in [%s]" % temp_dir)
+
+        task_ini_files = []
+        for eachfile in logfiles:
+            with open(eachfile) as fp:
+                run_dir = [re.findall(r'^INFO.*Run directory : (.*)$', line)
+                           for line in open(eachfile)]
+                run_dir = filter(bool, run_dir)
+                for each_run in run_dir:
+                    INIfile = os.path.join(each_run[0], args.ini_filename)
+                    if os.path.isfile(INIfile):
+                        task_ini_files.append(INIfile)
+        logger.info(f"Found {len(task_ini_files)} INI files")
+        run_modelsim(task_ini_files)
+
+
+def clean_up_and_exit(msg):
+    logger.error(msg)
+    logger.error("Exiting . . . . . .")
+    exit(1)
+
+
+def run_modelsim(files):
+    for eachFile in files:
         eachFile = os.path.abspath(eachFile)
         pDir = os.path.dirname(eachFile)
         os.chdir(pDir)
@@ -111,10 +177,10 @@ def main():
         # Execute modelsim
         if args.run_sim:
             os.chdir(args.modelsim_run_dir)
-            print(args.modelsim_run_dir)
             modelsim_run_cmd = ["vsim", "-c", "-do", runsim_filename]
-            run_command("ModelSim Run", "modelsim_run.log",
-                        modelsim_run_cmd)
+            out = run_command("ModelSim Run", "modelsim_run.log",
+                              modelsim_run_cmd)
+            logger.info(re.findall(r"(.*Errors.*Warning.*)", out))
         else:
             logger.info("Created runsim and proc files")
             logger.info(f"runsim_filename {runsim_filename}")

From 373dbe0718483ce5c773f41de5d8c645a7993a04 Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Sat, 16 Nov 2019 01:06:09 -0700
Subject: [PATCH 09/12] First draft for multithreaded Modelsim simulation

---
 openfpga_flow/scripts/run_modelsim.py | 130 ++++++++++++++++++--------
 1 file changed, 93 insertions(+), 37 deletions(-)

diff --git a/openfpga_flow/scripts/run_modelsim.py b/openfpga_flow/scripts/run_modelsim.py
index 2f4ac5fc4..cfbd76270 100644
--- a/openfpga_flow/scripts/run_modelsim.py
+++ b/openfpga_flow/scripts/run_modelsim.py
@@ -3,6 +3,9 @@ import sys
 import os
 import re
 import glob
+import time
+import threading
+from datetime import timedelta
 import argparse
 import subprocess
 import logging
@@ -11,6 +14,7 @@ from configparser import ConfigParser, ExtendedInterpolation
 # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
 # Configure logging system
 # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+FILE_LOG_FORMAT = '%(levelname)s (%(threadName)10s) - %(message)s'
 logging.basicConfig(level=logging.INFO, stream=sys.stdout,
                     format='%(levelname)s (%(threadName)10s) - %(message)s')
 logger = logging.getLogger('Modelsim_run_log')
@@ -22,6 +26,11 @@ parser = argparse.ArgumentParser()
 parser.add_argument('files', nargs='+',
                     help="Pass SimulationDeckInfo generated by OpenFPGA flow" +
                     " or pass taskname <taskname> <run_number[optional]>")
+parser.add_argument('--maxthreads', type=int, default=2,
+                    help="Number of fpga_flow threads to run default = 2," +
+                    "Typically <= Number of processors on the system")
+parser.add_argument('--debug', action="store_true",
+                    help="Run script in debug mode")
 parser.add_argument('--modelsim_proc_tmpl', type=str,
                     help="Modelsim proc template file")
 parser.add_argument('--modelsim_runsim_tmpl', type=str,
@@ -77,7 +86,7 @@ args.modelsim_runsim_tmpl = os.path.abspath(args.modelsim_runsim_tmpl)
 
 def main():
     if os.path.isfile(args.files[0]):
-        run_modelsim(args.files)
+        create_tcl_script(args.files)
     else:
         # Check if task directory exists and consistent
         taskname = args.files[0]
@@ -92,7 +101,17 @@ def main():
         if not os.path.isdir(temp_dir):
             clean_up_and_exit("Task run directory [%s] not found" % temp_dir)
 
-        logfile = os.path.join(gc["task_dir"], taskname, task_run, "*.log")
+        # = = = = = = = Create a current script log file handler = = = =
+        logfile_path = os.path.join(gc["task_dir"],
+                                    taskname, task_run, "modelsim_run.log")
+        logfilefh = logging.FileHandler(logfile_path, "w")
+        logfilefh.setFormatter(logging.Formatter(FILE_LOG_FORMAT))
+        logger.addHandler(logfilefh)
+        logger.info("Created log file at %s" % logfile_path)
+        # = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
+
+        # = = = = Read Task log file and extract run directory = = =
+        logfile = os.path.join(gc["task_dir"], taskname, task_run, "*_out.log")
         logfiles = glob.glob(logfile)
         if not len(logfiles):
             clean_up_and_exit("No successful run found in [%s]" % temp_dir)
@@ -108,7 +127,7 @@ def main():
                     if os.path.isfile(INIfile):
                         task_ini_files.append(INIfile)
         logger.info(f"Found {len(task_ini_files)} INI files")
-        run_modelsim(task_ini_files)
+        create_tcl_script(task_ini_files)
 
 
 def clean_up_and_exit(msg):
@@ -117,7 +136,8 @@ def clean_up_and_exit(msg):
     exit(1)
 
 
-def run_modelsim(files):
+def create_tcl_script(files):
+    runsim_files = []
     for eachFile in files:
         eachFile = os.path.abspath(eachFile)
         pDir = os.path.dirname(eachFile)
@@ -173,42 +193,78 @@ def run_modelsim(files):
         with open(proc_filename, 'w', encoding='utf-8') as tclout:
             tclout.write(open(args.modelsim_proc_tmpl,
                               encoding='utf-8').read())
-
-        # Execute modelsim
-        if args.run_sim:
-            os.chdir(args.modelsim_run_dir)
-            modelsim_run_cmd = ["vsim", "-c", "-do", runsim_filename]
-            out = run_command("ModelSim Run", "modelsim_run.log",
-                              modelsim_run_cmd)
-            logger.info(re.findall(r"(.*Errors.*Warning.*)", out))
-        else:
-            logger.info("Created runsim and proc files")
-            logger.info(f"runsim_filename {runsim_filename}")
-            logger.info(f"proc_filename {proc_filename}")
+        runsim_files.append({
+            "modelsim_run_dir": args.modelsim_run_dir,
+            "runsim_filename": runsim_filename,
+            "status" :False,
+            "finished" : True
+        })
+    # Execute modelsim
+    if args.run_sim:
+        thread_sema = threading.Semaphore(args.maxthreads)
+        logger.info("Launching %d parallel threads" % args.maxthreads)
+        thread_list = []
+        for thread_no, eachjob in enumerate(runsim_files):
+            t = threading.Thread(target=run_modelsim_thread,
+                                 name=f"Thread_{thread_no:d}",
+                                 args=(thread_sema, eachjob, runsim_files))
+            t.start()
+            thread_list.append(t)
+        for eachthread in thread_list:
+            eachthread.join()
+        exit()
+    else:
+        logger.info("Created runsim and proc files")
+        logger.info(f"runsim_filename {runsim_filename}")
+        logger.info(f"proc_filename {proc_filename}")
+        from pprint import pprint
+        pprint(runsim_files)
 
 
-def run_command(taskname, logfile, command, exit_if_fail=True):
-    # os.chdir(os.pardir)
-    logger.info("Launching %s " % taskname)
-    with open(logfile, 'w+') as output:
+def run_modelsim_thread(s, eachJob, job_list):
+    os.chdir(eachJob["modelsim_run_dir"])
+    with s:
+        thread_name = threading.currentThread().getName()
+        eachJob["starttime"] = time.time()
         try:
-            output.write(os.getcwd() + "\n")
-            output.write(" ".join(command)+"\n")
-            process = subprocess.run(command,
-                                     check=True,
-                                     stdout=subprocess.PIPE,
-                                     stderr=subprocess.PIPE,
-                                     universal_newlines=True)
-            output.write(process.stdout)
-            if process.returncode:
-                logger.error("%s run failed with returncode %d" %
-                             (taskname, process.returncode))
-        except (Exception, subprocess.CalledProcessError) as e:
-            logger.exception("failed to execute %s" % taskname)
-            return None
-    logger.info("%s is written in file %s" % (taskname, logfile))
-    return process.stdout
-
+            logfile = "%s_modelsim.log" % thread_name
+            with open(logfile, 'w+') as output:
+                output.write("* "*20 + '\n')
+                output.write("RunDirectory : %s\n" % os.getcwd())
+                command = ["vsim", "-c", "-do", eachJob["runsim_filename"]]
+                output.write(" ".join(command) + '\n')
+                output.write("* "*20 + '\n')
+                logger.info("Running modelsim with [%s]" % " ".join(command))
+                process = subprocess.Popen(command,
+                                           stdout=subprocess.PIPE,
+                                           stderr=subprocess.STDOUT,
+                                           universal_newlines=True)
+                for line in process.stdout:
+                    if "Errors" in line:
+                        logger.debug(line.strip())
+                    sys.stdout.buffer.flush()
+                    output.write(line)
+                process.wait()
+                if process.returncode:
+                    raise subprocess.CalledProcessError(0, " ".join(command))
+                eachJob["status"] = True
+        except:
+            logger.exception("Failed to execute openfpga flow - " +
+                             eachJob["name"])
+            if not args.continue_on_fail:
+                os._exit(1)
+        eachJob["endtime"] = time.time()
+        timediff = timedelta(seconds=(eachJob["endtime"]-eachJob["starttime"]))
+        timestr = humanize.naturaldelta(timediff) if "humanize" in sys.modules \
+            else str(timediff)
+        logger.info("%s Finished with returncode %d, Time Taken %s " %
+                    (thread_name, process.returncode, timestr))
+        eachJob["finished"] = True
+        no_of_finished_job = sum([not eachJ["finished"] for eachJ in job_list])
+        logger.info("***** %d runs pending *****" % (no_of_finished_job))
 
 if __name__ == "__main__":
+    if args.debug:
+        logger.info("Setting loggger in debug mode")
+        logger.setLevel(logging.DEBUG)
     main()

From 00ec36c1af79aea1f436082d4a0f36f6570fbd14 Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Sat, 16 Nov 2019 13:18:13 -0700
Subject: [PATCH 10/12] Added Modelsim error check in log

---
 openfpga_flow/scripts/run_modelsim.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/openfpga_flow/scripts/run_modelsim.py b/openfpga_flow/scripts/run_modelsim.py
index cfbd76270..173ff8494 100644
--- a/openfpga_flow/scripts/run_modelsim.py
+++ b/openfpga_flow/scripts/run_modelsim.py
@@ -241,7 +241,7 @@ def run_modelsim_thread(s, eachJob, job_list):
                                            universal_newlines=True)
                 for line in process.stdout:
                     if "Errors" in line:
-                        logger.debug(line.strip())
+                        logger.info(line.strip())
                     sys.stdout.buffer.flush()
                     output.write(line)
                 process.wait()

From cb1c7a8030bf8d42c38f156eba0203ae6d5f63be Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Sat, 16 Nov 2019 13:19:00 -0700
Subject: [PATCH 11/12] Added OpenFPGA bash function  utility

---
 openfpga.sh | 56 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100755 openfpga.sh

diff --git a/openfpga.sh b/openfpga.sh
new file mode 100755
index 000000000..fdf591a7c
--- /dev/null
+++ b/openfpga.sh
@@ -0,0 +1,56 @@
+#!/bin/bash
+#title           : openfpga.sh
+#description     : This script provides shortcut commands <bash functions>
+#                  for several simple operations in OpenFPGA project
+#author          : Ganesh Gore <ganesh.gore@utah.edu>
+#==============================================================================
+
+export OPENFPGA_PATH="$(pwd)"
+export OPENFPGA_TASK_PATH="$(pwd)/openfpga_flow/tasks"
+
+# This function checks the path and
+# raises warning if the command is not executing
+# inside current OpendFPGA folder
+check_execution_path (){
+    if [[ $1 != *"${OPENFPGA_PATH}"* ]]; then
+        echo -e "\e[33mCommand is not executed from configured OPNEFPGA directory\e[0m"
+    fi
+}
+
+# lists all the configure task in task directory
+list-tasks () {
+    check_execution_path "$(pwd)"
+    ls -tdalh ${OPENFPGA_TASK_PATH}/* | awk '{printf("%-4s | %s %-3s | ", $5, $6, $7) ;system("basename " $9)}'
+}
+
+# Switch directory to root of OpenFPGA
+goto-root () {
+    cd $OPENFPGA_PATH
+}
+
+# Changes directory to task directory [goto_task <task_name> <run_num[default 0]>]
+goto-task () {
+    if [ -z $1 ]; then
+        echo "requires task name goto_task <task_name> <run_num[default 0]>"
+        return
+    fi
+    goto_path=$OPENFPGA_TASK_PATH/$1
+    run_num="latest"
+    if [ ! -d $goto_path ]; then echo "Task directory not found"; return; fi
+    if [[ $2 == '^[0-9]+$' ]] ; then
+        echo "Second argumetn provided"
+        if ! [[ $2 == '0' ]] ; then run_num="$(printf run%03d $2)" else run_num="latest" fi
+        if [ ! -d "$goto_path/$run_num" ]; then run_num="latest" fi
+    fi
+    if [ ! -d $goto_path/$run_num ]; then
+        echo "\e[33mTask run directory not found -" $goto_path/$run_num "\e[0m";
+    else
+        cd $goto_path/$run_num
+    fi
+}
+
+# Clears enviroment variables and fucntions
+unset_openfpga (){
+    unset -v OPENFPGA_PATH
+    unset -f list-tasks goto-task goto-root >/dev/null 2>&1
+}
\ No newline at end of file

From bfb03af2c811f4a9411d9ca288a1c4a0030a1ea2 Mon Sep 17 00:00:00 2001
From: Ganesh Gore <goreganesh007@gmail.com>
Date: Sat, 16 Nov 2019 15:52:32 -0700
Subject: [PATCH 12/12] Added run-task and run-flow functions

---
 openfpga.sh | 36 +++++++++++++++++++++++++++---------
 1 file changed, 27 insertions(+), 9 deletions(-)

diff --git a/openfpga.sh b/openfpga.sh
index fdf591a7c..e44b22f82 100755
--- a/openfpga.sh
+++ b/openfpga.sh
@@ -6,7 +6,9 @@
 #==============================================================================
 
 export OPENFPGA_PATH="$(pwd)"
+export OPENFPGA_SCRIPT_PATH="$(pwd)/openfpga_flow/scripts"
 export OPENFPGA_TASK_PATH="$(pwd)/openfpga_flow/tasks"
+if [ -z $PYTHON_EXEC ]; then export PYTHON_EXEC="python3"; fi
 
 # This function checks the path and
 # raises warning if the command is not executing
@@ -17,6 +19,14 @@ check_execution_path (){
     fi
 }
 
+run-task () {
+    $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_task.py "$@"
+}
+
+run-flow () {
+    $PYTHON_EXEC $OPENFPGA_SCRIPT_PATH/run_fpga_flow.py "$@"
+}
+
 # lists all the configure task in task directory
 list-tasks () {
     check_execution_path "$(pwd)"
@@ -35,22 +45,30 @@ goto-task () {
         return
     fi
     goto_path=$OPENFPGA_TASK_PATH/$1
-    run_num="latest"
+    run_num=""
     if [ ! -d $goto_path ]; then echo "Task directory not found"; return; fi
-    if [[ $2 == '^[0-9]+$' ]] ; then
-        echo "Second argumetn provided"
-        if ! [[ $2 == '0' ]] ; then run_num="$(printf run%03d $2)" else run_num="latest" fi
-        if [ ! -d "$goto_path/$run_num" ]; then run_num="latest" fi
+    if [[ "$2" =~ '^[0-9]+$' ]] ; then
+        if ! [[ $2 == '0' ]] ; then run_num="$(printf run%03d $2)"; else run_num="latest"; fi
+        if [ ! -d "$goto_path/$run_num" ]; then run_num="latest"; fi
     fi
     if [ ! -d $goto_path/$run_num ]; then
-        echo "\e[33mTask run directory not found -" $goto_path/$run_num "\e[0m";
+        echo "\e[33mTask run directory not found -" $goto_path/$run_num "\e[0m"
     else
+        echo "Switching current dirctory to" $goto_path/$run_num
         cd $goto_path/$run_num
     fi
 }
 
 # Clears enviroment variables and fucntions
-unset_openfpga (){
+unset-openfpga (){
     unset -v OPENFPGA_PATH
-    unset -f list-tasks goto-task goto-root >/dev/null 2>&1
-}
\ No newline at end of file
+    unset -f list-tasks run-task run-flow goto-task goto-root >/dev/null 2>&1
+}
+
+# Allow autocompletion of task
+if [[ $(ps -p $$ -oargs=) == *"zsh"* ]]; then
+    autoload -U +X bashcompinit; bashcompinit;
+fi
+TaskList=$(ls -tdalh ${OPENFPGA_TASK_PATH}/* | awk '{system("basename " $9)}' |  awk '{printf("%s ",$1)}')
+complete -W "${TaskList}" goto-task
+complete -W "${TaskList}" run-task
\ No newline at end of file