From 3bf94b8e3462003abcdcc4f82bebf7d6fd123e2e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 22 Sep 2020 11:48:19 -0600 Subject: [PATCH] [Regression test] Remove no local routing from fpga verilog tests --- .travis/fpga_verilog_reg_test.sh | 3 -- .../no_local_routing/config/task.conf | 38 ------------------- 2 files changed, 41 deletions(-) delete mode 100644 openfpga_flow/tasks/fpga_verilog/no_local_routing/config/task.conf diff --git a/.travis/fpga_verilog_reg_test.sh b/.travis/fpga_verilog_reg_test.sh index f08ebed0e..ce8c57b92 100755 --- a/.travis/fpga_verilog_reg_test.sh +++ b/.travis/fpga_verilog_reg_test.sh @@ -96,9 +96,6 @@ python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/depopulate_crossbar echo -e "Testing Fully connected output crossbar in local routing"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/fully_connected_output_crossbar --debug --show_thread_logs -echo -e "Testing no local routing architecture"; -python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/no_local_routing --debug --show_thread_logs - echo -e "Testing through channels in tileable routing"; python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_narrow_tile --debug --show_thread_logs python3 openfpga_flow/scripts/run_fpga_task.py fpga_verilog/thru_channel/thru_wide_tile --debug --show_thread_logs diff --git a/openfpga_flow/tasks/fpga_verilog/no_local_routing/config/task.conf b/openfpga_flow/tasks/fpga_verilog/no_local_routing/config/task.conf deleted file mode 100644 index c076b156c..000000000 --- a/openfpga_flow/tasks/fpga_verilog/no_local_routing/config/task.conf +++ /dev/null @@ -1,38 +0,0 @@ -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# Configuration file for running experiments -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = -# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs -# Each job execute fpga_flow script on combination of architecture & benchmark -# timeout_each_job is timeout for each job -# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = - -[GENERAL] -run_engine=openfpga_shell -power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml -power_analysis = true -spice_output=false -verilog_output=true -timeout_each_job = 20*60 -fpga_flow=vpr_blif - -[OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_no_local_routing_40nm_frame_openfpga.xml -openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml -external_fabric_key_file= - -[ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_no_local_routing_40nm.xml - -[BENCHMARKS] -bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif - -[SYNTHESIS_PARAM] -bench0_top = and2 -bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act -bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v -bench0_chan_width = 300 - -[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -end_flow_with_test= -vpr_fpga_verilog_formal_verification_top_netlist=