From 3b6cd885f3f4c372a5b92e12a85faa12d17298f4 Mon Sep 17 00:00:00 2001 From: ganeshgore Date: Wed, 22 Jul 2020 11:57:04 -0600 Subject: [PATCH] BugFix: Fixed yosys_vpr with openFPGA_Shell --- openfpga_flow/scripts/run_fpga_flow.py | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index 9975a506d..9ab384cc4 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -419,6 +419,17 @@ def prepare_run_directory(run_dir): with open(args.openfpga_arch_file, 'w', encoding='utf-8') as archfile: archfile.write(tmpl.substitute(script_env_vars["PATH"])) + # Sanitize provided openshell template, if provided + if (args.openfpga_shell_template): + if not os.path.isfile(args.openfpga_shell_template or ""): + logger.error("Openfpga shell file - %s" % + args.openfpga_shell_template) + clean_up_and_exit("Provided openfpga_shell_template" + + f" {args.openfpga_shell_template} file not found") + else: + shutil.copy(args.openfpga_shell_template, + args.top_module+"_template.openfpga") + # Create benchmark dir in run_dir and copy flattern architecture file os.mkdir("benchmark") try: @@ -600,17 +611,6 @@ def collect_files_for_vpr(): clean_up_and_exit("Provided base_verilog file not found") shutil.copy(args.base_verilog, args.top_module+"_output_verilog.v") - # Sanitize provided openshell template, if provided - if (args.openfpga_shell_template): - if not os.path.isfile(args.openfpga_shell_template or ""): - logger.error("Openfpga shell file - %s" % - args.openfpga_shell_template) - clean_up_and_exit("Provided openfpga_shell_template" + - f" {args.openfpga_shell_template} file not found") - else: - shutil.copy(args.openfpga_shell_template, - args.top_module+"_template.openfpga") - def run_vpr(): ExecTime["VPRStart"] = time.time()