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Adding help message on the go.sh

This commit is contained in:
Baudouin Chauviere 2019-01-09 11:54:28 -07:00
parent 66701838ff
commit 3b4fc16c60
4 changed files with 4372 additions and 1 deletions
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vpr7_x2p/vpr/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml Normal file
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vpr7_x2p/vpr/ARCH/k6_N10_scan_chain_template.xml Normal file
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vpr7_x2p/vpr/ARCH/k6_N10_sram_ptm45nm_TT.xml Normal file
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vpr7_x2p/vpr/go.sh
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@ -2,18 +2,31 @@
# Example of how to run vprset circuit_name = pip_add # Example of how to run vprset circuit_name = pip_add
#set circuit_name = pip_add #set circuit_name = pip_add
set circuit_name = sync_4bits_add set circuit_name = sync_4bits_add
set arch_file = ${PWD}/ARCH/k6_N10_scan_chain_tsmc40nm_TT.xml
set circuit_blif = ${PWD}/Circuits/${circuit_name}.blif set circuit_blif = ${PWD}/Circuits/${circuit_name}.blif
set arch_file = ${PWD}/ARCH/k6_N10_scan_chain_ptm45nm_TT.xml
set arch_file_template = ${PWD}/ARCH/k6_N10_scan_chain_template.xml
set circuit_act = ${PWD}/Circuits/${circuit_name}.act set circuit_act = ${PWD}/Circuits/${circuit_name}.act
set circuit_verilog = ${PWD}/Circuits/${circuit_name}.v set circuit_verilog = ${PWD}/Circuits/${circuit_name}.v
set spice_output = ${PWD}/spice_demo set spice_output = ${PWD}/spice_demo
set verilog_output = ${PWD}/verilog_demo set verilog_output = ${PWD}/verilog_demo
set modelsim_ini = /uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini set modelsim_ini = /uusoc/facility/cad_tools/Mentor/modelsim10.7b/modeltech/modelsim.ini
set openfpga_path = ${PWD}/../..
# Make sure a clean start # Make sure a clean start
rm -rf ${spice_output} rm -rf ${spice_output}
rm -rf ${verilog_output} rm -rf ${verilog_output}
# Recreate the paths to direct to the right place
cp ${arch_file_template} ${arch_file}
sed 's/OPENFPGAPATH/"${openfpga_path}"/' ${arch_file}
echo "*******************************"
echo "THIS SCRIPT NEEDS TO BE SOURCED\n"
echo "source ./go.sh"
echo "*******************************"
# Pack, place, and route a heterogeneous FPGA # Pack, place, and route a heterogeneous FPGA
# Packing uses the AAPack algorithm # Packing uses the AAPack algorithm
./vpr ${arch_file} ${circuit_blif} --full_stats --nodisp --activity_file ${circuit_act} --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ${spice_output} --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ${verilog_output} --fpga_verilog_print_top_testbench --fpga_verilog_print_top_auto_testbench ${circuit_verilog} --fpga_verilog_print_modelsim_autodeck --fpga_verilog_modelsim_ini_path ${modelsim_ini} --fpga_verilog_include_timing --fpga_verilog_init_sim ./vpr ${arch_file} ${circuit_blif} --full_stats --nodisp --activity_file ${circuit_act} --route_chan_width 30 --fpga_spice --fpga_spice_rename_illegal_port --fpga_spice_dir ${spice_output} --fpga_spice_print_top_testbench --fpga_spice_print_grid_testbench --fpga_spice_print_cb_testbench --fpga_spice_print_sb_testbench --fpga_spice_print_lut_testbench --fpga_spice_print_hardlogic_testbench --fpga_spice_print_pb_mux_testbench --fpga_spice_print_cb_mux_testbench --fpga_spice_print_sb_mux_testbench --fpga_verilog --fpga_verilog_dir ${verilog_output} --fpga_verilog_print_top_testbench --fpga_verilog_print_top_auto_testbench ${circuit_verilog} --fpga_verilog_print_modelsim_autodeck --fpga_verilog_modelsim_ini_path ${modelsim_ini} --fpga_verilog_include_timing --fpga_verilog_init_sim