diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 9c493c9f7..b76631c5c 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -391,39 +391,35 @@ std::vector ClockNetwork::tree_flatten_taps( std::vector ClockNetwork::flatten_internal_driver_port(const ClockInternalDriverId& int_driver_id) const { std::vector flatten_taps; - for (const std::string& tap_name : internal_driver_port(int_driver_id)) { - StringToken tokenizer(tap_name); - std::vector pin_tokens = tokenizer.split("."); - if (pin_tokens.size() != 2) { - VTR_LOG_ERROR("Invalid pin name '%s'. Expect .\n", - tap_name.c_str()); - exit(1); - } - PortParser tile_parser(pin_tokens[0]); - BasicPort tile_info = tile_parser.port(); - PortParser pin_parser(pin_tokens[1]); - BasicPort pin_info = pin_parser.port(); - if (!tile_info.is_valid()) { - VTR_LOG_ERROR("Invalid pin name '%s' whose subtile index is not valid\n", - tap_name.c_str()); - exit(1); - } - if (!pin_info.is_valid()) { - VTR_LOG_ERROR("Invalid pin name '%s' whose pin index is not valid\n", - tap_name.c_str()); - exit(1); - } - for (size_t& tile_idx : tile_info.pins()) { - std::string flatten_tile_str = - tile_info.get_name() + "[" + std::to_string(tile_idx) + "]"; - for (size_t& pin_idx : pin_info.pins()) { - if (pin_idx != size_t(clk_pin_id)) { - continue; - } - std::string flatten_pin_str = - pin_info.get_name() + "[" + std::to_string(pin_idx) + "]"; - flatten_taps.push_back(flatten_tile_str + "." + flatten_pin_str); - } + std::string tap_name = internal_driver_port(int_driver_id); + StringToken tokenizer(tap_name); + std::vector pin_tokens = tokenizer.split("."); + if (pin_tokens.size() != 2) { + VTR_LOG_ERROR("Invalid pin name '%s'. Expect .\n", + tap_name.c_str()); + exit(1); + } + PortParser tile_parser(pin_tokens[0]); + BasicPort tile_info = tile_parser.port(); + PortParser pin_parser(pin_tokens[1]); + BasicPort pin_info = pin_parser.port(); + if (!tile_info.is_valid()) { + VTR_LOG_ERROR("Invalid pin name '%s' whose subtile index is not valid\n", + tap_name.c_str()); + exit(1); + } + if (!pin_info.is_valid()) { + VTR_LOG_ERROR("Invalid pin name '%s' whose pin index is not valid\n", + tap_name.c_str()); + exit(1); + } + for (size_t& tile_idx : tile_info.pins()) { + std::string flatten_tile_str = + tile_info.get_name() + "[" + std::to_string(tile_idx) + "]"; + for (size_t& pin_idx : pin_info.pins()) { + std::string flatten_pin_str = + pin_info.get_name() + "[" + std::to_string(pin_idx) + "]"; + flatten_taps.push_back(flatten_tile_str + "." + flatten_pin_str); } } return flatten_taps; diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index 3263c838b..ecfe5e874 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -565,7 +565,7 @@ static void add_rr_graph_block_clock_edges( static void try_find_and_add_clock_opin2track_node( std::vector& opin_nodes, const DeviceGrid& grids, const RRGraphView& rr_graph_view, const size_t& layer, - const vtr::Point& grid_coord, const e_side& pin_side, + const vtr::Point& grid_coord, const e_side& pin_side, const ClockNetwork& clk_ntwk, const ClockInternalDriverId& int_driver_id) { t_physical_tile_type_ptr grid_type = grids.get_physical_type( @@ -624,14 +624,14 @@ static std::vector find_clock_opin2track_node( * - Grid[x+1][y] on left and top sides */ std::array, 4> grid_coords; - std::array, 2>, 4> grid_sides; - grid_coords[0] = grid_coord(sb_coord.x(), sb_coord.y() + 1); + std::array, 4> grid_sides; + grid_coords[0] = vtr::Point(sb_coord.x(), sb_coord.y() + 1); grid_sides[0] = {RIGHT, BOTTOM}; - grid_coords[1] = grid_coord(sb_coord.x() + 1, sb_coord.y() + 1); + grid_coords[1] = vtr::Point(sb_coord.x() + 1, sb_coord.y() + 1); grid_sides[1] = {LEFT, BOTTOM}; - grid_coords[2] = grid_coord(sb_coord.x() + 1, sb_coord.y()); + grid_coords[2] = vtr::Point(sb_coord.x() + 1, sb_coord.y()); grid_sides[2] = {RIGHT, TOP}; - grid_coords[3] = grid_coord(sb_coord.x(), sb_coord.y()); + grid_coords[3] = vtr::Point(sb_coord.x(), sb_coord.y()); grid_sides[3] = {LEFT, TOP}; for (size_t igrid = 0; igrid < 4; igrid++) { vtr::Point grid_coord = grid_coords[igrid]; @@ -657,38 +657,40 @@ static int add_rr_graph_opin2clk_edges(RRGraphBuilder& rr_graph_builder, size_t& const DeviceGrid& grids, const size_t& layer, const ClockNetwork& clk_ntwk, const bool& verbose) { size_t edge_count = 0; - for (ClockSpineId ispine : clk_ntwk.spines(clk_tree)) { - VTR_LOGV(verbose, "Finding internal drivers on spine '%s'...\n", - clk_ntwk.spine_name(ispine).c_str()); - for (auto ipin : clk_ntwk.pins(clk_tree)) { - for (ClockSwitchPointId switch_point_id : - clk_ntwk.spine_switch_points(ispine)) { - if (clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id).empty()) { - continue; /* We only focus on switching points containing internal drivers */ + for (ClockTreeId clk_tree : clk_ntwk.trees()) { + for (ClockSpineId ispine : clk_ntwk.spines(clk_tree)) { + VTR_LOGV(verbose, "Finding internal drivers on spine '%s'...\n", + clk_ntwk.spine_name(ispine).c_str()); + for (auto ipin : clk_ntwk.pins(clk_tree)) { + for (ClockSwitchPointId switch_point_id : + clk_ntwk.spine_switch_points(ispine)) { + if (clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id).empty()) { + continue; /* We only focus on switching points containing internal drivers */ + } + size_t curr_edge_count = edge_count; + /* Get the rr node of destination spine */ + ClockSpineId des_spine = + clk_ntwk.spine_switch_point_tap(ispine, switch_point_id); + vtr::Point des_coord = clk_ntwk.spine_start_point(des_spine); + Direction des_spine_direction = clk_ntwk.spine_direction(des_spine); + ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine); + RRNodeId des_node = + clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, + des_spine_level, ipin, des_spine_direction); + /* Walk through each qualified OPIN, build edges */ + vtr::Point src_coord = + clk_ntwk.spine_switch_point(ispine, switch_point_id); + std::vector int_driver_ids = clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id); + for (RRNodeId src_node : find_clock_opin2track_node(grids, rr_graph_view, layer, src_coord, clk_ntwk, int_driver_ids)) { + /* Create edges */ + VTR_ASSERT(rr_graph_view.valid_node(des_node)); + rr_graph_builder.create_edge(src_node, des_node, + clk_ntwk.default_driver_switch(), false); + edge_count++; + } + VTR_LOGV(verbose, "\tWill add %lu edges to OPINs at (x=%lu, y=%lu)\n", + edge_count - curr_edge_count, des_coord.x(), des_coord.y()); } - size_t curr_edge_count = edge_count; - /* Get the rr node of destination spine */ - ClockSpineId des_spine = - clk_ntwk.spine_switch_point_tap(ispine, switch_point_id); - vtr::Point des_coord = clk_ntwk.spine_start_point(des_spine); - Direction des_spine_direction = clk_ntwk.spine_direction(des_spine); - ClockLevelId des_spine_level = clk_ntwk.spine_level(des_spine); - RRNodeId des_node = - clk_rr_lookup.find_node(des_coord.x(), des_coord.y(), clk_tree, - des_spine_level, ipin, des_spine_direction); - /* Walk through each qualified OPIN, build edges */ - vtr::Point src_coord = - clk_ntwk.spine_switch_point(ispine, switch_point_id); - std::vector int_driver_ids = clk_ntwk.spine_switch_point_internal_drivers(ispine, switch_point_id); - for (RRNodId src_node : find_clock_opin2track_node(grids, rr_graph_view, layer, src_coord, clk_ntwk, int_driver_ids)) { - /* Create edges */ - VTR_ASSERT(rr_graph_view.valid_node(des_node)); - rr_graph_builder.create_edge(src_node, des_node, - clk_ntwk.default_driver_switch(), false); - edge_count++; - } - VTR_LOGV(verbose, "\tWill add %lu edges to OPINs at (x=%lu, y=%lu)\n", - edge_count - curr_edge_count, des_coord.x(), des_coord.y()); } } } @@ -756,7 +758,7 @@ static void add_rr_graph_clock_edges( } } /* Add edges between OPIN (internal driver) and clock routing tracks */ - add_rr_graph_opin2clk_edges(rr_graph_builder, num_edges_to_create, rr_graph_view, grids, layer, clk_ntwk, verbose); + add_rr_graph_opin2clk_edges(rr_graph_builder, num_edges_to_create, clk_rr_lookup, rr_graph_view, grids, layer, clk_ntwk, verbose); } /********************************************************************