riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[lib] syntax

This commit is contained in:
tangxifan 2024-06-26 15:51:00 -07:00
parent 381a8cb535
commit 3b25e42720
4 changed files with 20 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
libs/libclkarchopenfpga/src/base/clock_network.cpp
View File

@ -703,8 +703,7 @@ ClockInternalDriverId ClockNetwork::add_spine_switch_point_internal_driver(
ClockTapId ClockNetwork::add_tree_tap(const ClockTreeId& tree_id, ClockTapId ClockNetwork::add_tree_tap(const ClockTreeId& tree_id,
const std::string& from_port, const std::string& from_port,
const std::string& to_port, const std::string& to_port) {
const ) {
VTR_ASSERT(valid_tree_id(tree_id)); VTR_ASSERT(valid_tree_id(tree_id));
/* TODO: Consider find existing tap template and avoid duplication in storage */ /* TODO: Consider find existing tap template and avoid duplication in storage */
ClockTapId tap_id = ClockTapId(tap_ids_.size()); ClockTapId tap_id = ClockTapId(tap_ids_.size());
@ -712,7 +711,7 @@ ClockTapId ClockNetwork::add_tree_tap(const ClockTreeId& tree_id,
tap_from_ports_.push_back(from_port); tap_from_ports_.push_back(from_port);
tap_to_ports_.push_back(to_port); tap_to_ports_.push_back(to_port);
tap_bbs_.emplace_back(empty_tap_bb_); tap_bbs_.emplace_back(empty_tap_bb_);
tap_bb_steps_.emplace_back(vtr::Point<size_t>(1, 1)); tap_bb_steps_.emplace_back(vtr::Point<size_t>(0, 0));
tree_taps_[tree_id].push_back(tap_id); tree_taps_[tree_id].push_back(tap_id);
return tap_id; return tap_id;
} }
@ -720,7 +719,7 @@ ClockTapId ClockNetwork::add_tree_tap(const ClockTreeId& tree_id,
bool ClockNetwork::set_tap_bounding_box(const ClockTapId& tap_id, const vtr::Rect<size_t>& bb) { bool ClockNetwork::set_tap_bounding_box(const ClockTapId& tap_id, const vtr::Rect<size_t>& bb) {
VTR_ASSERT(valid_tap_id(tap_id)); VTR_ASSERT(valid_tap_id(tap_id));
/* Check the bounding box, ensure it must be valid */ /* Check the bounding box, ensure it must be valid */
if (bb.height() < 0 || bb.width() < 0) { if (bb.xmax() < bb.xmin() || bb.ymax() < bb.ymin()) {
VTR_LOG_ERROR("Invalid bounding box (xlow=%lu, ylow=%lu) -> (xhigh=%lu, yhigh=%lu)! Must follow: xlow <= xhigh, ylow <= yhigh!\n", bb.xmin(), bb.ymin(), bb.xmax(), bb.ymax()); VTR_LOG_ERROR("Invalid bounding box (xlow=%lu, ylow=%lu) -> (xhigh=%lu, yhigh=%lu)! Must follow: xlow <= xhigh, ylow <= yhigh!\n", bb.xmin(), bb.ymin(), bb.xmax(), bb.ymax());
return false; return false;
} }
@ -728,25 +727,25 @@ bool ClockNetwork::set_tap_bounding_box(const ClockTapId& tap_id, const vtr::Rec
return true; return true;
} }
bool ClockNetwork::set_tap_step_x(const ClockTapId& tap_id, const size_t step) { bool ClockNetwork::set_tap_step_x(const ClockTapId& tap_id, const size_t& step) {
VTR_ASSERT(valid_tap_id(tap_id)); VTR_ASSERT(valid_tap_id(tap_id));
/* Must be a valid step >= 1 */ /* Must be a valid step >= 1 */
if (step == 0) { if (step == 0) {
VTR_LOG_ERROR("Invalid x-direction step (=%lu) for any bounding box! Expect an integer >= 1!\n", step); VTR_LOG_ERROR("Invalid x-direction step (=%lu) for any bounding box! Expect an integer >= 1!\n", step);
return false; return false;
} }
tap_bbs_[tap_id].set_x(step); tap_bb_steps_[tap_id].set_x(step);
return true; return true;
} }
bool ClockNetwork::set_tap_step_y(const ClockTapId& tap_id, const size_t step) { bool ClockNetwork::set_tap_step_y(const ClockTapId& tap_id, const size_t& step) {
VTR_ASSERT(valid_tap_id(tap_id)); VTR_ASSERT(valid_tap_id(tap_id));
/* Must be a valid step >= 1 */ /* Must be a valid step >= 1 */
if (step == 0) { if (step == 0) {
VTR_LOG_ERROR("Invalid y-direction step (=%lu) for any bounding box! Expect an integer >= 1!\n", step); VTR_LOG_ERROR("Invalid y-direction step (=%lu) for any bounding box! Expect an integer >= 1!\n", step);
return false; return false;
} }
tap_bbs_[tap_id].set_y(step); tap_bb_steps_[tap_id].set_y(step);
return true; return true;
} }

4
libs/libclkarchopenfpga/src/base/clock_network.h
View File

@ -49,7 +49,7 @@ class ClockNetwork {
typedef vtr::Range<clock_internal_driver_iterator> typedef vtr::Range<clock_internal_driver_iterator>
clock_internal_driver_range; clock_internal_driver_range;
/* Type of tap points */ /* Type of tap points */
enum class : unsigned char { enum class e_tap_type : unsigned char {
ALL = 0, ALL = 0,
SINGLE, SINGLE,
REGION, REGION,
@ -284,7 +284,7 @@ class ClockNetwork {
vtr::vector<ClockTreeId, size_t> tree_widths_; vtr::vector<ClockTreeId, size_t> tree_widths_;
vtr::vector<ClockTreeId, size_t> tree_depths_; vtr::vector<ClockTreeId, size_t> tree_depths_;
vtr::vector<ClockTreeId, std::vector<ClockSpineId>> tree_top_spines_; vtr::vector<ClockTreeId, std::vector<ClockSpineId>> tree_top_spines_;
vtr::vector<ClockTreeId, ClockTapId> tree_taps_; vtr::vector<ClockTreeId, std::vector<ClockTapId>> tree_taps_;
/* Basic information of each spine */ /* Basic information of each spine */
vtr::vector<ClockSpineId, ClockSpineId> spine_ids_; vtr::vector<ClockSpineId, ClockSpineId> spine_ids_;

12
libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp
View File

@ -67,10 +67,10 @@ static void read_xml_clock_tree_tap_type_single(pugi::xml_node& xml_tap,
/* Single tap only require a coordinate */ /* Single tap only require a coordinate */
size_t tap_x = size_t tap_x =
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_X, loc_data, pugi::ReqOpt::REQUIRED) get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_X, loc_data, pugiutil::ReqOpt::REQUIRED)
.as_int(); .as_int();
size_t tap_y = size_t tap_y =
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_Y, loc_data, pugi::ReqOpt::REQUIRED) get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_Y, loc_data, pugiutil::ReqOpt::REQUIRED)
.as_int(); .as_int();
clk_ntwk.set_tap_bounding_box(tap_id, vtr::Rect<size_t>(tap_x, tap_y, tap_x, tap_y)); clk_ntwk.set_tap_bounding_box(tap_id, vtr::Rect<size_t>(tap_x, tap_y, tap_x, tap_y));
} }
@ -97,16 +97,16 @@ static void read_xml_clock_tree_tap_type_region(pugi::xml_node& xml_tap,
/* Region require a bounding box */ /* Region require a bounding box */
size_t tap_start_x = size_t tap_start_x =
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX, loc_data, pugi::ReqOpt::REQUIRED) get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTX, loc_data, pugiutil::ReqOpt::REQUIRED)
.as_int(); .as_int();
size_t tap_start_y = size_t tap_start_y =
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTY, loc_data, pugi::ReqOpt::REQUIRED) get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_STARTY, loc_data, pugiutil::ReqOpt::REQUIRED)
.as_int(); .as_int();
size_t tap_end_x = size_t tap_end_x =
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDX, loc_data, pugi::ReqOpt::REQUIRED) get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDX, loc_data, pugiutil::ReqOpt::REQUIRED)
.as_int(); .as_int();
size_t tap_end_y = size_t tap_end_y =
get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDY, loc_data, pugi::ReqOpt::REQUIRED) get_attribute(xml_tap, XML_CLOCK_TREE_TAP_ATTRIBUTE_ENDY, loc_data, pugiutil::ReqOpt::REQUIRED)
.as_int(); .as_int();
clk_ntwk.set_tap_bounding_box(tap_id, vtr::Rect<size_t>(tap_start_x, tap_start_y, tap_end_x, tap_end_y)); clk_ntwk.set_tap_bounding_box(tap_id, vtr::Rect<size_t>(tap_start_x, tap_start_y, tap_end_x, tap_end_y));

6
libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp
View File

@ -30,7 +30,7 @@ static int write_xml_clock_tree_taps(std::fstream& fp,
fp << "<" << XML_CLOCK_TREE_TAPS_NODE_NAME << ">\n"; fp << "<" << XML_CLOCK_TREE_TAPS_NODE_NAME << ">\n";
/* Depends on the type */ /* Depends on the type */
for (ClockTapId tap_id : clk_ntwk.tree_taps(tree_id)) { for (ClockTapId tap_id : clk_ntwk.tree_taps(tree_id)) {
switch clk_ntwk.tap_type(tap_id): { switch (clk_ntwk.tap_type(tap_id)) {
case ClockNetwork::e_tap_type::ALL: { case ClockNetwork::e_tap_type::ALL: {
openfpga::write_tab_to_file(fp, 4); openfpga::write_tab_to_file(fp, 4);
fp << "<" << XML_CLOCK_TREE_TAP_ALL_NODE_NAME << ""; fp << "<" << XML_CLOCK_TREE_TAP_ALL_NODE_NAME << "";
@ -40,6 +40,7 @@ static int write_xml_clock_tree_taps(std::fstream& fp,
clk_ntwk.tap_to_port(tap_id).c_str()); clk_ntwk.tap_to_port(tap_id).c_str());
fp << "/>" fp << "/>"
<< "\n"; << "\n";
break;
} }
case ClockNetwork::e_tap_type::SINGLE: { case ClockNetwork::e_tap_type::SINGLE: {
openfpga::write_tab_to_file(fp, 4); openfpga::write_tab_to_file(fp, 4);
@ -54,6 +55,7 @@ static int write_xml_clock_tree_taps(std::fstream& fp,
clk_ntwk.tap_y(tap_id)); clk_ntwk.tap_y(tap_id));
fp << "/>" fp << "/>"
<< "\n"; << "\n";
break;
} }
case ClockNetwork::e_tap_type::REGION: { case ClockNetwork::e_tap_type::REGION: {
openfpga::write_tab_to_file(fp, 4); openfpga::write_tab_to_file(fp, 4);
@ -76,12 +78,14 @@ static int write_xml_clock_tree_taps(std::fstream& fp,
clk_ntwk.tap_step_y(tap_id)); clk_ntwk.tap_step_y(tap_id));
fp << "/>" fp << "/>"
<< "\n"; << "\n";
break;
} }
default: { default: {
VTR_LOG_ERROR("Invalid type of tap point!\n"); VTR_LOG_ERROR("Invalid type of tap point!\n");
return 1; return 1;
} }
} }
}
openfpga::write_tab_to_file(fp, 3); openfpga::write_tab_to_file(fp, 3);
fp << "</" << XML_CLOCK_TREE_TAPS_NODE_NAME << ">\n"; fp << "</" << XML_CLOCK_TREE_TAPS_NODE_NAME << ">\n";