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Finish renaming SCFF to CCFF

This commit is contained in:
AurelienUoU 2019-09-26 14:04:40 -06:00
parent c4449b667f
commit 3b13c959f3
4 changed files with 15 additions and 15 deletions
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2
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_bitstream_utils.h
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@ -30,7 +30,7 @@ int count_num_reserved_conf_bit_one_interc(t_interconnect* cur_interc,
enum e_sram_orgz cur_sram_orgz_type);
void
add_mux_scff_conf_bits_to_llist(int mux_size,
add_mux_ccff_conf_bits_to_llist(int mux_size,
t_sram_orgz_info* cur_sram_orgz_info,
int num_mux_sram_bits, int* mux_sram_bits,
t_spice_model* mux_spice_model);

14
vpr7_x2p/vpr/SRC/fpga_x2p/base/fpga_x2p_naming.cpp
View File

@ -418,20 +418,20 @@ std::string generate_sram_local_port_name(const CircuitLibrary& circuit_lib,
}
case SPICE_SRAM_SCAN_CHAIN:
/* Three types of ports are available:
* (1) Input of Scan-chain Flip-Flops (SCFFs), enabled by port type of INPUT
* (2) Output of a chian of Scan-chain Flip-flops (SCFFs), enabled by port type of OUTPUT
* (2) Inverted output of a chian of Scan-chain Flip-flops (SCFFs), enabled by port type of INOUT
* (1) Input of Configuration-chain Flip-Flops (CCFFs), enabled by port type of INPUT
* (2) Output of a chian of Configuration-chain Flip-flops (CCFFs), enabled by port type of OUTPUT
* (2) Inverted output of a chian of Configuration-chain Flip-flops (CCFFs), enabled by port type of INOUT
* +------+ +------+ +------+
* Head --->| SCFF |--->| SCFF |--->| SCFF |---> Tail
* Head --->| CCFF |--->| CCFF |--->| CCFF |---> Tail
* +------+ +------+ +------+
*/
if (SPICE_MODEL_PORT_INPUT == port_type) {
port_name += std::string("scff_in_local_bus");
port_name += std::string("ccff_in_local_bus");
} else if ( SPICE_MODEL_PORT_OUTPUT == port_type ) {
port_name += std::string("scff_out_local_bus");
port_name += std::string("ccff_out_local_bus");
} else {
VTR_ASSERT( SPICE_MODEL_PORT_INOUT == port_type );
port_name += std::string("scff_outb_local_bus");
port_name += std::string("ccff_outb_local_bus");
}
break;
case SPICE_SRAM_MEMORY_BANK: {

12
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_decoders.cpp
View File

@ -222,7 +222,7 @@ void print_verilog_submodule_mux_local_decoders(ModuleManager& module_manager,
* which connect configuration ports to SRAMs/CCFFs in a chain:
*
* +------+ +------+ +------+
* sc_in--->| CCFF |--->| CCFF |---> ... --->| CCFF |----> sc_out
* cc_in--->| CCFF |--->| CCFF |---> ... --->| CCFF |----> sc_out
* +------+ +------+ +------+
***************************************************************************************/
static
@ -246,8 +246,8 @@ void print_verilog_scan_chain_config_module(ModuleManager& module_manager,
BasicPort sc_head_port(std::string(top_netlist_scan_chain_head_prefix), 1);
module_manager.add_port(module_id, sc_head_port, ModuleManager::MODULE_INPUT_PORT);
/* Add the inputs of scan-chain FFs, which are the outputs of the module */
BasicPort sc_input_port(std::string("chain_input"), num_mem_bits);
module_manager.add_port(module_id, sc_input_port, ModuleManager::MODULE_OUTPUT_PORT);
BasicPort cc_input_port(std::string("chain_input"), num_mem_bits);
module_manager.add_port(module_id, cc_input_port, ModuleManager::MODULE_OUTPUT_PORT);
/* Add the outputs of scan-chain FFs, which are inputs of the module */
BasicPort sc_output_port(std::string("chain_output"), num_mem_bits);
module_manager.add_port(module_id, sc_output_port, ModuleManager::MODULE_INPUT_PORT);
@ -261,11 +261,11 @@ void print_verilog_scan_chain_config_module(ModuleManager& module_manager,
fp << std::endl;
/* Connect scan-chain input to the first scan-chain input */
BasicPort sc_first_input_port(sc_input_port.get_name(), 1);
BasicPort sc_first_input_port(cc_input_port.get_name(), 1);
print_verilog_wire_connection(fp, sc_first_input_port, sc_head_port, false);
/* Connect the head of current ccff to the tail of previous ccff*/
BasicPort chain_output_port(sc_input_port.get_name(), 1, num_mem_bits - 1);
BasicPort chain_output_port(cc_input_port.get_name(), 1, num_mem_bits - 1);
BasicPort chain_input_port(sc_output_port.get_name(), 0, num_mem_bits - 2);
print_verilog_wire_connection(fp, chain_output_port, chain_input_port, false);
@ -285,7 +285,7 @@ void print_verilog_scan_chain_config_module(ModuleManager& module_manager,
* as a chain:
*
* +------+ +------+ +------+
* sc_in--->| CCFF |--->| CCFF |---> ... --->| CCFF |----> sc_out
* cc_in--->| CCFF |--->| CCFF |---> ... --->| CCFF |----> sc_out
* +------+ +------+ +------+
*
* 2. Memory bank:

2
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_global.c
View File

@ -131,7 +131,7 @@ char* top_netlist_normal_bl_port_postfix = "_bl";
char* top_netlist_normal_wl_port_postfix = "_wl";
char* top_netlist_normal_blb_port_postfix = "_blb";
char* top_netlist_normal_wlb_port_postfix = "_wlb";
char* top_netlist_scan_chain_head_prefix = "sc_in";
char* top_netlist_scan_chain_head_prefix = "cc_in";
char* top_tb_reset_port_name = "greset";
char* top_tb_set_port_name = "gset";