From 3afb92d6a5f5c92294fbdf0481eb732086473f9a Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 30 Jun 2024 22:48:15 -0700 Subject: [PATCH] [core] code format --- libs/libarchopenfpga/src/tile_annotation.cpp | 1 - .../src/base/clock_network.cpp | 3 +- .../src/base/clock_network.h | 5 +- .../src/io/read_xml_clock_network.cpp | 11 +++-- .../src/io/write_xml_clock_network.cpp | 5 +- .../src/annotation/route_clock_rr_graph.cpp | 49 ++++++++++++------- .../src/annotation/route_clock_rr_graph.h | 4 +- .../src/base/openfpga_link_arch_template.h | 3 +- .../fabric/build_top_module_connection.cpp | 6 ++- 9 files changed, 52 insertions(+), 35 deletions(-) diff --git a/libs/libarchopenfpga/src/tile_annotation.cpp b/libs/libarchopenfpga/src/tile_annotation.cpp index c6c71c4b2..77adcff18 100644 --- a/libs/libarchopenfpga/src/tile_annotation.cpp +++ b/libs/libarchopenfpga/src/tile_annotation.cpp @@ -101,7 +101,6 @@ bool TileAnnotation::global_port_thru_dedicated_network( return !global_port_clock_arch_tree_name(global_port_id).empty(); } - std::string TileAnnotation::global_port_clock_arch_tree_name( const TileGlobalPortId& global_port_id) const { VTR_ASSERT(valid_global_port_id(global_port_id)); diff --git a/libs/libclkarchopenfpga/src/base/clock_network.cpp b/libs/libclkarchopenfpga/src/base/clock_network.cpp index 1d3ab5b47..6f254530b 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.cpp +++ b/libs/libclkarchopenfpga/src/base/clock_network.cpp @@ -640,7 +640,8 @@ void ClockNetwork::set_default_driver_switch_name(const std::string& name) { default_driver_switch_name_ = name; } -ClockTreeId ClockNetwork::create_tree(const std::string& name, const BasicPort& global_port) { +ClockTreeId ClockNetwork::create_tree(const std::string& name, + const BasicPort& global_port) { /* Sanity checks */ if (!global_port.is_valid()) { VTR_LOG_ERROR("Invalid global port '%s' for clock tree name '%s'\n", diff --git a/libs/libclkarchopenfpga/src/base/clock_network.h b/libs/libclkarchopenfpga/src/base/clock_network.h index 7775b6fbf..242720dce 100644 --- a/libs/libclkarchopenfpga/src/base/clock_network.h +++ b/libs/libclkarchopenfpga/src/base/clock_network.h @@ -14,9 +14,9 @@ /* Headers from openfpgautil library */ #include "clock_network_fwd.h" +#include "openfpga_port.h" #include "rr_graph_fwd.h" #include "rr_node_types.h" -#include "openfpga_port.h" namespace openfpga { // Begin namespace openfpga @@ -198,7 +198,8 @@ class ClockNetwork { void set_default_driver_switch_name(const std::string& name); /* Create a new tree, by default the tree can accomodate only 1 clock signal; * use width to adjust the size */ - ClockTreeId create_tree(const std::string& name, const BasicPort& global_port); + ClockTreeId create_tree(const std::string& name, + const BasicPort& global_port); /* Create a new spine, if the spine is already created, return an invalid id */ ClockSpineId create_spine(const std::string& name); diff --git a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp index 84aea0587..4d47ad18e 100644 --- a/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp @@ -338,15 +338,18 @@ static void read_xml_clock_tree(pugi::xml_node& xml_clk_tree, const pugiutil::loc_data& loc_data, ClockNetwork& clk_ntwk) { std::string clk_tree_name = - get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_NAME, loc_data, pugiutil::ReqOpt::REQUIRED) + get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_NAME, loc_data, + pugiutil::ReqOpt::REQUIRED) .as_string(); std::string clk_global_port_str = - get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_GLOBAL_PORT, loc_data, pugiutil::ReqOpt::REQUIRED) + get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_GLOBAL_PORT, loc_data, + pugiutil::ReqOpt::REQUIRED) .as_string(); /* Create a new tree in the storage */ - PortParser gport_parser(clk_global_port_str); - ClockTreeId tree_id = clk_ntwk.create_tree(clk_tree_name, gport_parser.port()); + PortParser gport_parser(clk_global_port_str); + ClockTreeId tree_id = + clk_ntwk.create_tree(clk_tree_name, gport_parser.port()); if (false == clk_ntwk.valid_tree_id(tree_id)) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_clk_tree), diff --git a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp index 5ef8e4d3d..3473a6350 100644 --- a/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp +++ b/libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp @@ -194,8 +194,9 @@ static int write_xml_clock_tree(std::fstream& fp, const ClockNetwork& clk_ntwk, write_xml_attribute(fp, XML_CLOCK_TREE_ATTRIBUTE_NAME, clk_ntwk.tree_name(tree_id).c_str()); - write_xml_attribute(fp, XML_CLOCK_TREE_ATTRIBUTE_GLOBAL_PORT, - clk_ntwk.tree_global_port(tree_id).to_verilog_string().c_str()); + write_xml_attribute( + fp, XML_CLOCK_TREE_ATTRIBUTE_GLOBAL_PORT, + clk_ntwk.tree_global_port(tree_id).to_verilog_string().c_str()); fp << ">" << "\n"; diff --git a/openfpga/src/annotation/route_clock_rr_graph.cpp b/openfpga/src/annotation/route_clock_rr_graph.cpp index fb4afda93..0be7cdf84 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.cpp +++ b/openfpga/src/annotation/route_clock_rr_graph.cpp @@ -26,7 +26,8 @@ static int build_clock_tree_net_map( const ClockTreeId clk_tree, const bool& verbose) { BasicPort tree_gport = clk_ntwk.tree_global_port(clk_tree); /* Find the pin id for each clock name, error out if there is any mismatch */ - if (clk_ntwk.num_trees() == 1 && gnets.size() == 1 && clk_ntwk.tree_width(clk_tree) == 1) { + if (clk_ntwk.num_trees() == 1 && gnets.size() == 1 && + clk_ntwk.tree_width(clk_tree) == 1) { /* Find cluster net id */ if (!cluster_nlist.valid_net_id(gnets[0])) { VTR_LOG_ERROR("Invalid clock name '%s'! Cannot be found from netlists!\n", @@ -42,7 +43,8 @@ static int build_clock_tree_net_map( BasicPort tree_pin = pin_constraints.net_pin(gnet_name); if (!tree_pin.is_valid()) { VTR_LOG_ERROR( - "Global net '%s' is not mapped to a valid pin '%s' in pin constraints!\n", + "Global net '%s' is not mapped to a valid pin '%s' in pin " + "constraints!\n", gnet_name.c_str(), tree_pin.to_verilog_string().c_str()); return CMD_EXEC_FATAL_ERROR; } @@ -59,17 +61,20 @@ static int build_clock_tree_net_map( } if (!tree_gport.contained(tree_pin)) { VTR_LOG_ERROR( - "Invalid pin constraint port '%s' which is out of range of the global port '%s' of clock tree '%s'\n", + "Invalid pin constraint port '%s' which is out of range of the " + "global port '%s' of clock tree '%s'\n", tree_pin.to_verilog_string().c_str(), tree_gport.to_verilog_string().c_str(), clk_ntwk.tree_name(clk_tree).c_str()); return CMD_EXEC_FATAL_ERROR; } - /* TODO: Check the tree_pin.get_name(), see if matches the tree from ports */ + /* TODO: Check the tree_pin.get_name(), see if matches the tree from ports + */ /* Register the pin mapping */ tree2clk_pin_map[ClockTreePinId(tree_pin.get_lsb())] = gnet; VTR_LOGV(verbose, "Mapped net '%s' to pin '%s' of clock tree '%s'.\n", - gnet_name.c_str(), tree_pin.to_verilog_string().c_str(), clk_ntwk.tree_name(clk_tree).c_str()); + gnet_name.c_str(), tree_pin.to_verilog_string().c_str(), + clk_ntwk.tree_name(clk_tree).c_str()); } } @@ -186,8 +191,10 @@ static int route_spine_taps( size_t spine_tap_cnt = 0; /* Route the spine-to-IPIN connections (only for the last level) */ if (clk_ntwk.is_last_level(ispine)) { - VTR_LOGV(verbose, "Routing clock taps of spine '%s' for pin '%d' of tree '%s'...\n", - clk_ntwk.spine_name(ispine).c_str(), size_t(ipin), clk_ntwk.tree_name(clk_tree).c_str()); + VTR_LOGV(verbose, + "Routing clock taps of spine '%s' for pin '%d' of tree '%s'...\n", + clk_ntwk.spine_name(ispine).c_str(), size_t(ipin), + clk_ntwk.tree_name(clk_tree).c_str()); /* Connect to any fan-out node which is IPIN */ for (size_t icoord = 0; icoord < spine_coords.size(); ++icoord) { vtr::Point src_coord = spine_coords[icoord]; @@ -397,11 +404,13 @@ static int rec_expand_and_route_clock_spine( src_coord.y(), des_coord.x(), des_coord.y()); vpr_routing_annotation.set_rr_node_prev_node(rr_graph, des_node, src_node); /* It could happen that there is no net mapped some clock pin, skip the - * net mapping */ - if (tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { - vpr_routing_annotation.set_rr_node_net(src_node, tree2clk_pin_map.at(curr_pin)); - vpr_routing_annotation.set_rr_node_net(des_node, tree2clk_pin_map.at(curr_pin)); - } + * net mapping */ + if (tree2clk_pin_map.find(curr_pin) != tree2clk_pin_map.end()) { + vpr_routing_annotation.set_rr_node_net(src_node, + tree2clk_pin_map.at(curr_pin)); + vpr_routing_annotation.set_rr_node_net(des_node, + tree2clk_pin_map.at(curr_pin)); + } prev_stop_usage = true; curr_spine_usage = true; @@ -463,11 +472,10 @@ static int route_clock_tree_rr_graph( *******************************************************************/ int route_clock_rr_graph( VprRoutingAnnotation& vpr_routing_annotation, - const DeviceContext& vpr_device_ctx, - const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, + const DeviceContext& vpr_device_ctx, const ClusteredNetlist& cluster_nlist, + const PlacementContext& vpr_place_ctx, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, - const PinConstraints& pin_constraints, - const bool& disable_unused_trees, + const PinConstraints& pin_constraints, const bool& disable_unused_trees, const bool& disable_unused_spines, const bool& verbose) { vtr::ScopedStartFinishTimer timer( "Route programmable clock network based on routing resource graph"); @@ -482,10 +490,12 @@ int route_clock_rr_graph( /* If there are multiple global signals from the netlist, require pin * constraints */ - std::vector gnets = find_clustered_netlist_global_nets(cluster_nlist); + std::vector gnets = + find_clustered_netlist_global_nets(cluster_nlist); if (gnets.empty()) { VTR_LOG( - "Skip due to 0 global nets found from netlist\nDouble check your HDL design " + "Skip due to 0 global nets found from netlist\nDouble check your HDL " + "design " "if this is unexpected\n"); return CMD_EXEC_SUCCESS; } @@ -504,7 +514,8 @@ int route_clock_rr_graph( /* Route spines one by one */ for (auto itree : clk_ntwk.trees()) { - VTR_LOGV(verbose, "Build global net name to clock tree '%s' pin mapping...\n", + VTR_LOGV(verbose, + "Build global net name to clock tree '%s' pin mapping...\n", clk_ntwk.tree_name(itree).c_str()); std::map tree2clk_pin_map; int status = CMD_EXEC_SUCCESS; diff --git a/openfpga/src/annotation/route_clock_rr_graph.h b/openfpga/src/annotation/route_clock_rr_graph.h index 443e3d11b..2bd4ec178 100644 --- a/openfpga/src/annotation/route_clock_rr_graph.h +++ b/openfpga/src/annotation/route_clock_rr_graph.h @@ -19,8 +19,8 @@ namespace openfpga { int route_clock_rr_graph( VprRoutingAnnotation& vpr_routing_annotation, - const DeviceContext& vpr_device_ctx, - const ClusteredNetlist& cluster_nlist, const PlacementContext& vpr_place_ctx, + const DeviceContext& vpr_device_ctx, const ClusteredNetlist& cluster_nlist, + const PlacementContext& vpr_place_ctx, const RRClockSpatialLookup& clk_rr_lookup, const ClockNetwork& clk_ntwk, const PinConstraints& pin_constraints, const bool& disable_unused_trees, const bool& disable_unused_spines, const bool& verbose); diff --git a/openfpga/src/base/openfpga_link_arch_template.h b/openfpga/src/base/openfpga_link_arch_template.h index cfb5b430f..bb061de09 100644 --- a/openfpga/src/base/openfpga_link_arch_template.h +++ b/openfpga/src/base/openfpga_link_arch_template.h @@ -234,8 +234,7 @@ int route_clock_rr_graph_template(T& openfpga_ctx, const Command& cmd, return route_clock_rr_graph( openfpga_ctx.mutable_vpr_routing_annotation(), g_vpr_ctx.device(), g_vpr_ctx.clustering().clb_nlist, g_vpr_ctx.placement(), - openfpga_ctx.clock_rr_lookup(), - openfpga_ctx.clock_arch(), pin_constraints, + openfpga_ctx.clock_rr_lookup(), openfpga_ctx.clock_arch(), pin_constraints, cmd_context.option_enable(cmd, opt_disable_unused_trees), cmd_context.option_enable(cmd, opt_disable_unused_spines), cmd_context.option_enable(cmd, opt_verbose)); diff --git a/openfpga/src/fabric/build_top_module_connection.cpp b/openfpga/src/fabric/build_top_module_connection.cpp index e0c86ab17..e6a98cd46 100644 --- a/openfpga/src/fabric/build_top_module_connection.cpp +++ b/openfpga/src/fabric/build_top_module_connection.cpp @@ -1324,8 +1324,10 @@ int add_top_module_global_ports_from_grid_modules( global_port_to_add.set_name( tile_annotation.global_port_name(tile_global_port)); /* Dedicated network has their own sizes of port */ - if (tile_annotation.global_port_thru_dedicated_network(tile_global_port)) { - std::string clk_tree_name = tile_annotation.global_port_clock_arch_tree_name(tile_global_port); + if (tile_annotation.global_port_thru_dedicated_network( + tile_global_port)) { + std::string clk_tree_name = + tile_annotation.global_port_clock_arch_tree_name(tile_global_port); ClockTreeId clk_tree = clk_ntwk.find_tree(clk_tree_name); global_port_to_add.set_width(clk_ntwk.tree_width(clk_tree)); } else {