add advanced check in configurable memories

libopenfpga/libarchopenfpga/src/check_circuit_library.cpp

@@ -552,3 +552,4 @@ bool check_circuit_library(const CircuitLibrary& circuit_lib) {
 
   return true;
 }
+

openfpga/src/base/openfpga_read_arch.cpp

@@ -11,6 +11,7 @@
 /* Headers from archopenfpga library */
 #include "read_xml_openfpga_arch.h"
 #include "check_circuit_library.h"
+#include "circuit_library_utils.h"
 #include "write_xml_openfpga_arch.h"
 
 #include "openfpga_read_arch.h"
@@ -50,6 +51,12 @@ int read_arch(OpenfpgaContext& openfpga_context,
     return CMD_EXEC_FATAL_ERROR;
   }
 
+  if (false == check_configurable_memory_circuit_model(openfpga_context.arch().config_protocol.type(),
+                                                       openfpga_context.arch().circuit_lib,
+                                                       openfpga_context.arch().config_protocol.memory_model())) {
+    return CMD_EXEC_FATAL_ERROR;
+  }
+
   return CMD_EXEC_SUCCESS;
 } 
 

openfpga/src/utils/circuit_library_utils.cpp

@@ -11,6 +11,7 @@
 #include "vtr_assert.h"
 #include "vtr_log.h"
 
+#include "check_circuit_library.h"
 #include "circuit_library_utils.h"
 
 /* begin namespace openfpga */
@@ -226,4 +227,40 @@ std::vector<std::string> find_circuit_library_unique_verilog_netlists(const Circ
  return netlists;
 }
 
+/************************************************************************
+ * Advanced check if the circuit model of configurable memory
+ * satisfy the needs of configuration protocol
+ * - Configuration chain -based: we check if we have a CCFF model
+ * - Frame -based: we check if we have a SRAM model which has BL and WL
+ * 
+ ***********************************************************************/
+bool check_configurable_memory_circuit_model(const e_config_protocol_type& config_protocol_type,
+                                             const CircuitLibrary& circuit_lib,
+                                             const CircuitModelId& config_mem_circuit_model) {
+  size_t num_err = 0;
+
+  switch (config_protocol_type) {
+  case CONFIG_MEM_SCAN_CHAIN:   
+    num_err = check_ccff_circuit_model_ports(circuit_lib,
+                                             config_mem_circuit_model);
+    break;
+  case CONFIG_MEM_STANDALONE: 
+  case CONFIG_MEM_MEMORY_BANK:  
+  case CONFIG_MEM_FRAME_BASED:  
+    num_err = check_sram_circuit_model_ports(circuit_lib,
+                                             config_mem_circuit_model,
+                                             true);
+    
+    break;
+  default:
+    VTR_LOGF_ERROR(__FILE__, __LINE__,
+                   "Invalid type of configuration protocol!\n");
+    return false;
+  }
+  
+  VTR_LOG("Found %ld errors when checking configurable memory circuit models!\n",
+          num_err);
+  return (0 == num_err);
+}
+
 } /* end namespace openfpga */

openfpga/src/utils/circuit_library_utils.h

@@ -38,6 +38,10 @@ std::vector<CircuitPortId> find_circuit_library_global_ports(const CircuitLibrar
 
 std::vector<std::string> find_circuit_library_unique_verilog_netlists(const CircuitLibrary& circuit_lib);
 
+bool check_configurable_memory_circuit_model(const e_config_protocol_type& config_protocol_type,
+                                             const CircuitLibrary& circuit_lib,
+                                             const CircuitModelId& config_mem_circuit_model);
+
 } /* end namespace openfpga */
 
 #endif