[core] adding prog clock arch support for tile modules
This commit is contained in:
tangxifan
parent
0f3f4b0d81
commit
399259ea1d
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@ -1054,6 +1054,476 @@ static void organize_top_module_tile_based_memory_modules(
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config_protocol);
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config_protocol);
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}
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}
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/*********************************************************************
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* Generate an input port for routing multiplexer inside the tile
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* which is the middle output of a routing track
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********************************************************************/
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ModulePinInfo find_tile_module_chan_port(
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const ModuleManager& module_manager, const ModuleId& tile_module,
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const vtr::Point<size_t>& cb_coord_in_tile,
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const RRGraphView& rr_graph, const RRGSB& rr_gsb, const t_rr_type& cb_type,
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const RRNodeId& chan_rr_node) {
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ModulePinInfo input_port_info;
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/* Generate the input port object */
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switch (rr_graph.node_type(chan_rr_node)) {
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case CHANX:
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case CHANY: {
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/* Create port description for the routing track middle output */
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int chan_node_track_id =
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rr_gsb.get_cb_chan_node_index(cb_type, chan_rr_node);
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/* Create a port description for the middle output */
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std::string input_port_name = generate_cb_module_track_port_name(
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cb_type, IN_PORT, 0 == chan_node_track_id % 2);
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std::string tile_input_port_name = generate_tile_module_port_name(generate_connection_block_module_name(cb_type, cb_coord_in_tile), input_port_name);
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/* Must find a valid port id in the Switch Block module */
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input_port_info.first =
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module_manager.find_module_port(tile_module, tile_input_port_name);
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input_port_info.second = chan_node_track_id / 2;
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VTR_ASSERT(true == module_manager.valid_module_port_id(
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tile_module, input_port_info.first));
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break;
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}
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default: /* OPIN, SOURCE, IPIN, SINK are invalid*/
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VTR_LOGF_ERROR(__FILE__, __LINE__,
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"Invalid rr_node type! Should be [OPIN|CHANX|CHANY].\n");
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exit(1);
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}
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return input_port_info;
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}
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/********************************************************************
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* Add nets between a global port and its sinks at an entry point of clock tree
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*******************************************************************/
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static int build_top_module_global_net_from_tile_clock_arch_tree(
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ModuleManager& module_manager, const ModuleId& top_module,
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const ModulePortId& top_module_port, const RRGraphView& rr_graph,
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const DeviceRRGSB& device_rr_gsb,
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const vtr::Matrix<size_t>& tile_instance_ids,
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const FabricTile& fabric_tile,
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const ClockNetwork& clk_ntwk, const std::string& clk_tree_name,
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const RRClockSpatialLookup& rr_clock_lookup) {
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int status = CMD_EXEC_SUCCESS;
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/* Ensure the clock arch tree name is valid */
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ClockTreeId clk_tree = clk_ntwk.find_tree(clk_tree_name);
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if (!clk_ntwk.valid_tree_id(clk_tree)) {
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VTR_LOG(
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"Fail to find a matched clock tree '%s' in the clock architecture "
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"definition",
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clk_tree_name.c_str());
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return CMD_EXEC_FATAL_ERROR;
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}
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/* Ensure the clock tree width matches the global port size */
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if (clk_ntwk.tree_width(clk_tree) !=
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module_manager.module_port(top_module, top_module_port).get_width()) {
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VTR_LOG(
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"Clock tree '%s' does not have the same width '%lu' as the port '%'s of "
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"FPGA top module",
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clk_tree_name.c_str(), clk_ntwk.tree_width(clk_tree),
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module_manager.module_port(top_module, top_module_port)
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.get_name()
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.c_str());
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return CMD_EXEC_FATAL_ERROR;
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}
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for (ClockTreePinId pin : clk_ntwk.pins(clk_tree)) {
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BasicPort src_port =
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module_manager.module_port(top_module, top_module_port);
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/* Add the module net */
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ModuleNetId net = create_module_source_pin_net(
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module_manager, top_module, top_module, 0, top_module_port,
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src_port.pins()[size_t(pin)]);
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VTR_ASSERT(ModuleNetId::INVALID() != net);
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for (ClockSpineId spine : clk_ntwk.tree_top_spines(clk_tree)) {
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vtr::Point<int> entry_point = clk_ntwk.spine_start_point(spine);
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Direction entry_dir = clk_ntwk.spine_direction(spine);
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t_rr_type entry_track_type = clk_ntwk.spine_track_type(spine);
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/* Find the routing resource node of the entry point */
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RRNodeId entry_rr_node =
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rr_clock_lookup.find_node(entry_point.x(), entry_point.y(), clk_tree,
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clk_ntwk.spine_level(spine), pin, entry_dir);
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/* Get the tile module and instance at the entry point */
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const RRGSB& rr_gsb = device_rr_gsb.get_gsb_by_cb_coordinate(
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entry_track_type, vtr::Point<size_t>(entry_point.x(), entry_point.y()));
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vtr::Point<size_t> cb_coord_in_tile = rr_gsb.get_sb_coordinate();
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FabricTileId curr_fabric_tile_id = fabric_tile.find_tile_by_cb_coordinate(entry_track_type, cb_coord_in_tile);
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vtr::Point<size_t> curr_fabric_tile_coord = fabric_tile.tile_coordinate(curr_fabric_tile_id);
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FabricTileId unique_fabric_tile_id = fabric_tile.unique_tile(curr_fabric_tile_coord);
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vtr::Point<size_t> unique_fabric_tile_coord = fabric_tile.tile_coordinate(unique_fabric_tile_id);
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ModuleId tile_module = module_manager.find_module(generate_tile_module_name(unique_fabric_tile_coord));
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size_t tile_instance = tile_instance_ids[curr_fabric_tile_coord.x()][curr_fabric_tile_coord.y()];
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/* Find the port name */
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size_t cb_idx_in_curr_fabric_tile = fabric_tile.find_cb_index_in_tile(curr_fabric_tile_id, entry_track_type, cb_coord_in_tile);
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vtr::Point<size_t> cb_coord_in_unique_fabric_tile = fabric_tile.cb_coordinates(unique_fabric_tile_id, entry_track_type)[cb_idx_in_curr_fabric_tile];
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ModulePinInfo des_pin_info = find_tile_module_chan_port(
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module_manager, tile_module, cb_coord_in_unique_fabric_tile, rr_graph, rr_gsb, entry_track_type,
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entry_rr_node);
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/* Configure the net sink */
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BasicPort sink_port =
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module_manager.module_port(tile_module, des_pin_info.first);
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module_manager.add_module_net_sink(top_module, net, tile_module,
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tile_instance, des_pin_info.first,
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sink_port.pins()[des_pin_info.second]);
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}
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}
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return status;
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}
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/********************************************************************
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* Add global port connection for a given port of a physical tile
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* that are defined as global in tile annotation
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*******************************************************************/
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static int build_top_module_global_net_for_given_tile_module(
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ModuleManager& module_manager, const ModuleId& top_module,
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const ModulePortId& top_module_port, const TileAnnotation& tile_annotation,
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const TileGlobalPortId& tile_global_port,
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const BasicPort& tile_port_to_connect,
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const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
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const vtr::Point<size_t>& grid_coordinate, const e_side& border_side,
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const vtr::Matrix<size_t>& grid_instance_ids) {
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t_physical_tile_type_ptr physical_tile =
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grids.get_physical_type(grid_coordinate.x(), grid_coordinate.y());
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/* Find the module name for this type of grid */
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std::string grid_module_name_prefix(GRID_MODULE_NAME_PREFIX);
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std::string grid_module_name = generate_grid_block_module_name(
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grid_module_name_prefix, std::string(physical_tile->name),
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is_io_type(physical_tile), border_side);
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ModuleId grid_module = module_manager.find_module(grid_module_name);
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VTR_ASSERT(true == module_manager.valid_module_id(grid_module));
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size_t grid_instance =
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grid_instance_ids[grid_coordinate.x()][grid_coordinate.y()];
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/* Find the source port at the top-level module */
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BasicPort src_port = module_manager.module_port(top_module, top_module_port);
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/* Walk through each instance considering the unique sub tile and capacity
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* range, each instance may have an independent pin to be driven by a global
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* net! */
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for (const t_sub_tile& sub_tile : physical_tile->sub_tiles) {
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VTR_ASSERT(1 == sub_tile.equivalent_sites.size());
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int grid_pin_start_index = physical_tile->num_pins;
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t_physical_tile_port physical_tile_port;
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physical_tile_port.num_pins = 0;
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/* Count the total number of pins for this type of sub tile */
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int sub_tile_num_pins = sub_tile.num_phy_pins / sub_tile.capacity.total();
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/* For each instance of the same sub tile type, find the port of the grid
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* module according to the tile annotation A tile may consist of multiple
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* subtile, connect to all the pins from sub tiles */
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for (int subtile_index = sub_tile.capacity.low;
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subtile_index <= sub_tile.capacity.high; subtile_index++) {
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for (const t_physical_tile_port& tile_port : sub_tile.ports) {
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if (std::string(tile_port.name) == tile_port_to_connect.get_name()) {
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BasicPort ref_tile_port(tile_port.name, tile_port.num_pins);
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/* Port size must match!!! */
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if (false == ref_tile_port.contained(tile_port_to_connect)) {
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VTR_LOG_ERROR(
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"Tile annotation '%s' port '%s[%lu:%lu]' is out of the range of "
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"physical tile port '%s[%lu:%lu]'!",
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tile_annotation.global_port_name(tile_global_port).c_str(),
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tile_port_to_connect.get_name().c_str(),
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tile_port_to_connect.get_lsb(), tile_port_to_connect.get_msb(),
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ref_tile_port.get_name().c_str(), ref_tile_port.get_lsb(),
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ref_tile_port.get_msb());
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return CMD_EXEC_FATAL_ERROR;
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}
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grid_pin_start_index =
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(subtile_index - sub_tile.capacity.low) * sub_tile_num_pins +
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tile_port.absolute_first_pin_index;
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physical_tile_port = tile_port;
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break;
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}
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}
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/* Ensure the pin index is valid */
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VTR_ASSERT(grid_pin_start_index < physical_tile->num_pins);
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/* Ensure port width is in range */
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VTR_ASSERT(src_port.get_width() == tile_port_to_connect.get_width());
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/* Create a pin id mapping between the source port (top module) and the
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* sink port (grid module) */
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std::map<size_t, size_t> sink2src_pin_map;
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for (size_t ipin = 0; ipin < tile_port_to_connect.get_width(); ++ipin) {
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size_t sink_pin = tile_port_to_connect.pins()[ipin];
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size_t src_pin = src_port.pins()[ipin];
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sink2src_pin_map[sink_pin] = src_pin;
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}
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/* Create the connections */
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for (size_t pin_id = tile_port_to_connect.get_lsb();
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pin_id < tile_port_to_connect.get_msb() + 1; ++pin_id) {
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int grid_pin_index = grid_pin_start_index + pin_id;
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/* Find the module pin */
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size_t grid_pin_width = physical_tile->pin_width_offset[grid_pin_index];
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size_t grid_pin_height =
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physical_tile->pin_height_offset[grid_pin_index];
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std::vector<e_side> pin_sides = find_physical_tile_pin_side(
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physical_tile, grid_pin_index, border_side);
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BasicPort grid_pin_info =
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vpr_device_annotation.physical_tile_pin_port_info(physical_tile,
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grid_pin_index);
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VTR_ASSERT(true == grid_pin_info.is_valid());
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/* Build nets */
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for (const e_side& pin_side : pin_sides) {
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std::string grid_port_name =
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generate_grid_port_name(grid_pin_width, grid_pin_height,
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subtile_index, pin_side, grid_pin_info);
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ModulePortId grid_port_id =
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module_manager.find_module_port(grid_module, grid_port_name);
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VTR_ASSERT(true == module_manager.valid_module_port_id(grid_module,
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grid_port_id));
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VTR_ASSERT(
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1 ==
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module_manager.module_port(grid_module, grid_port_id).get_width());
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ModuleNetId net = create_module_source_pin_net(
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module_manager, top_module, top_module, 0, top_module_port,
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src_port.pins()[sink2src_pin_map[pin_id]]);
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VTR_ASSERT(ModuleNetId::INVALID() != net);
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/* Configure the net sink */
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BasicPort sink_port =
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module_manager.module_port(grid_module, grid_port_id);
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module_manager.add_module_net_sink(top_module, net, grid_module,
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grid_instance, grid_port_id,
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sink_port.pins()[0]);
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}
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}
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}
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}
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return CMD_EXEC_SUCCESS;
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}
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/********************************************************************
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* Add nets between a global port and its sinks at each tile modules
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*******************************************************************/
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static int build_top_module_global_net_from_tile_modules(
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ModuleManager& module_manager, const ModuleId& top_module,
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const ModulePortId& top_module_port, const TileAnnotation& tile_annotation,
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const TileGlobalPortId& tile_global_port,
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const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
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const vtr::Matrix<size_t>& tile_instance_ids,
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const FabricTile& fabric_tile) {
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int status = CMD_EXEC_SUCCESS;
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std::map<e_side, std::vector<vtr::Point<size_t>>> io_coordinates =
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generate_perimeter_grid_coordinates(grids);
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for (size_t tile_info_id = 0;
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tile_info_id <
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tile_annotation.global_port_tile_names(tile_global_port).size();
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++tile_info_id) {
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std::string tile_name =
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tile_annotation.global_port_tile_names(tile_global_port)[tile_info_id];
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BasicPort tile_port =
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tile_annotation.global_port_tile_ports(tile_global_port)[tile_info_id];
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/* Find the coordinates for the wanted tiles */
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vtr::Point<size_t> start_coord(1, 1);
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vtr::Point<size_t> end_coord(grids.width() - 1, grids.height() - 1);
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vtr::Point<size_t> range = tile_annotation.global_port_tile_coordinates(
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tile_global_port)[tile_info_id];
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bool out_of_range = false;
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/* -1 means all the x should be considered */
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if (size_t(-1) != range.x()) {
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if ((range.x() < start_coord.x()) || (range.x() > end_coord.x())) {
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out_of_range = true;
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} else {
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/* Set the range */
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start_coord.set_x(range.x());
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end_coord.set_x(range.x());
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}
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}
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/* -1 means all the y should be considered */
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if (size_t(-1) != range.y()) {
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if ((range.y() < start_coord.y()) || (range.y() > end_coord.y())) {
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out_of_range = true;
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} else {
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/* Set the range */
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start_coord.set_y(range.y());
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end_coord.set_y(range.y());
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}
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}
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/* Error out immediately if the coordinate is not valid! */
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if (true == out_of_range) {
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VTR_LOG_ERROR(
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"Coordinate (%lu, %lu) in tile annotation for tile '%s' is out of "
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"range (%lu:%lu, %lu:%lu)!",
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range.x(), range.y(), tile_name.c_str(), start_coord.x(), end_coord.x(),
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start_coord.y(), end_coord.y());
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return CMD_EXEC_FATAL_ERROR;
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}
|
||||||
|
|
||||||
|
/* Spot the port from child modules from core grids */
|
||||||
|
for (size_t ix = start_coord.x(); ix < end_coord.x(); ++ix) {
|
||||||
|
for (size_t iy = start_coord.y(); iy < end_coord.y(); ++iy) {
|
||||||
|
t_physical_tile_type_ptr phy_tile_type =
|
||||||
|
grids.get_physical_type(ix, iy);
|
||||||
|
/* Bypass EMPTY tiles */
|
||||||
|
if (true == is_empty_type(phy_tile_type)) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
/* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
|
||||||
|
if ((0 < grids.get_width_offset(ix, iy)) ||
|
||||||
|
(0 < grids.get_height_offset(ix, iy))) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Bypass the tiles whose names do not match */
|
||||||
|
if (std::string(phy_tile_type->name) != tile_name) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Create nets and finish connection build-up */
|
||||||
|
status = build_top_module_global_net_for_given_tile_module(
|
||||||
|
module_manager, top_module, top_module_port, tile_annotation,
|
||||||
|
tile_global_port, tile_port, vpr_device_annotation, grids,
|
||||||
|
vtr::Point<size_t>(ix, iy), NUM_SIDES, grid_instance_ids);
|
||||||
|
if (CMD_EXEC_FATAL_ERROR == status) {
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Walk through all the grids on the perimeter, which are I/O grids */
|
||||||
|
for (const e_side& io_side : FPGA_SIDES_CLOCKWISE) {
|
||||||
|
for (const vtr::Point<size_t>& io_coordinate : io_coordinates[io_side]) {
|
||||||
|
t_physical_tile_type_ptr phy_tile_type =
|
||||||
|
grids.get_physical_type(io_coordinate.x(), io_coordinate.y());
|
||||||
|
/* Bypass EMPTY grid */
|
||||||
|
if (true == is_empty_type(phy_tile_type)) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Skip width or height > 1 tiles (mostly heterogeneous blocks) */
|
||||||
|
if ((0 <
|
||||||
|
grids.get_width_offset(io_coordinate.x(), io_coordinate.y())) ||
|
||||||
|
(0 <
|
||||||
|
grids.get_height_offset(io_coordinate.x(), io_coordinate.y()))) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Bypass the tiles whose names do not match */
|
||||||
|
if (std::string(phy_tile_type->name) != tile_name) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check if the coordinate satisfy the tile coordinate defintion
|
||||||
|
* - Bypass if the x is a specific number (!= -1), and io_coordinate
|
||||||
|
* is different
|
||||||
|
* - Bypass if the y is a specific number (!= -1), and io_coordinate
|
||||||
|
* is different
|
||||||
|
*/
|
||||||
|
if ((size_t(-1) != range.x()) && (range.x() != io_coordinate.x())) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
if ((size_t(-1) != range.y()) && (range.y() != io_coordinate.y())) {
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Create nets and finish connection build-up */
|
||||||
|
status = build_top_module_global_net_for_given_tile_module(
|
||||||
|
module_manager, top_module, top_module_port, tile_annotation,
|
||||||
|
tile_global_port, tile_port, vpr_device_annotation, grids,
|
||||||
|
io_coordinate, io_side, grid_instance_ids);
|
||||||
|
if (CMD_EXEC_FATAL_ERROR == status) {
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
|
/********************************************************************
|
||||||
|
* Add global ports from tile ports that are defined as global in tile
|
||||||
|
*annotation
|
||||||
|
*******************************************************************/
|
||||||
|
static int add_top_module_global_ports_from_tile_modules(
|
||||||
|
ModuleManager& module_manager, const ModuleId& top_module,
|
||||||
|
const TileAnnotation& tile_annotation,
|
||||||
|
const VprDeviceAnnotation& vpr_device_annotation, const DeviceGrid& grids,
|
||||||
|
const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb,
|
||||||
|
const vtr::Matrix<size_t>& tile_instance_ids,
|
||||||
|
const FabricTile& fabric_tile, const ClockNetwork& clk_ntwk,
|
||||||
|
const RRClockSpatialLookup& rr_clock_lookup) {
|
||||||
|
int status = CMD_EXEC_SUCCESS;
|
||||||
|
|
||||||
|
/* Add the global ports which are NOT yet added to the top-level module
|
||||||
|
* (in different names than the global ports defined in circuit library
|
||||||
|
*/
|
||||||
|
std::vector<BasicPort> global_ports_to_add;
|
||||||
|
for (const TileGlobalPortId& tile_global_port :
|
||||||
|
tile_annotation.global_ports()) {
|
||||||
|
ModulePortId module_port = module_manager.find_module_port(
|
||||||
|
top_module, tile_annotation.global_port_name(tile_global_port));
|
||||||
|
/* The global port size is derived from the maximum port size among all the
|
||||||
|
* tile port defintion */
|
||||||
|
if (ModulePortId::INVALID() == module_port) {
|
||||||
|
BasicPort global_port_to_add;
|
||||||
|
global_port_to_add.set_name(
|
||||||
|
tile_annotation.global_port_name(tile_global_port));
|
||||||
|
size_t max_port_size = 0;
|
||||||
|
for (const BasicPort& tile_port :
|
||||||
|
tile_annotation.global_port_tile_ports(tile_global_port)) {
|
||||||
|
max_port_size = std::max(tile_port.get_width(), max_port_size);
|
||||||
|
}
|
||||||
|
global_port_to_add.set_width(max_port_size);
|
||||||
|
global_ports_to_add.push_back(global_port_to_add);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
for (const BasicPort& global_port_to_add : global_ports_to_add) {
|
||||||
|
module_manager.add_port(top_module, global_port_to_add,
|
||||||
|
ModuleManager::MODULE_GLOBAL_PORT);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Add module nets */
|
||||||
|
for (const TileGlobalPortId& tile_global_port :
|
||||||
|
tile_annotation.global_ports()) {
|
||||||
|
/* Must found one valid port! */
|
||||||
|
ModulePortId top_module_port = module_manager.find_module_port(
|
||||||
|
top_module, tile_annotation.global_port_name(tile_global_port));
|
||||||
|
VTR_ASSERT(ModulePortId::INVALID() != top_module_port);
|
||||||
|
|
||||||
|
/* There are two cases when building the nets:
|
||||||
|
* - If the net will go through a dedicated clock tree network, the net will
|
||||||
|
* drive an input of a routing block
|
||||||
|
* - If the net will be directly wired to tiles, the net will drive an input
|
||||||
|
* of a tile
|
||||||
|
*/
|
||||||
|
if (!tile_annotation.global_port_clock_arch_tree_name(tile_global_port)
|
||||||
|
.empty()) {
|
||||||
|
status = build_top_module_global_net_from_tile_clock_arch_tree(
|
||||||
|
module_manager, top_module, top_module_port, rr_graph, device_rr_gsb,
|
||||||
|
tile_instance_ids, fabric_tile, clk_ntwk,
|
||||||
|
tile_annotation.global_port_clock_arch_tree_name(tile_global_port),
|
||||||
|
rr_clock_lookup);
|
||||||
|
} else {
|
||||||
|
status = build_top_module_global_net_from_tile_modules(
|
||||||
|
module_manager, top_module, top_module_port, tile_annotation,
|
||||||
|
tile_global_port, vpr_device_annotation, grids, tile_instance_ids, fabric_tile);
|
||||||
|
}
|
||||||
|
if (status == CMD_EXEC_FATAL_ERROR) {
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return status;
|
||||||
|
}
|
||||||
|
|
||||||
/********************************************************************
|
/********************************************************************
|
||||||
* Add the tile-level instances to the top module of FPGA fabric
|
* Add the tile-level instances to the top module of FPGA fabric
|
||||||
|
|
@ -1092,14 +1562,14 @@ int build_top_module_tile_child_instances(
|
||||||
/* TODO: Inter-tile direct connections */
|
/* TODO: Inter-tile direct connections */
|
||||||
}
|
}
|
||||||
|
|
||||||
/* TODO: Add global ports from tile modules: how to connect to clock
|
/* TODO: Add global ports from tile modules: how to connect to clock architecture and the global port from tile annotation
|
||||||
architecture and the global port from tile annotation status =
|
*/
|
||||||
add_top_module_global_ports_from_grid_modules( module_manager, top_module,
|
status = add_top_module_global_ports_from_tile_modules( module_manager, top_module,
|
||||||
tile_annotation, vpr_device_annotation, grids, rr_graph, device_rr_gsb,
|
tile_annotation, vpr_device_annotation, grids, rr_graph, device_rr_gsb,
|
||||||
cb_instance_ids, grid_instance_ids, clk_ntwk, rr_clock_lookup); if
|
tile_instance_ids, fabric_tile, clk_ntwk, rr_clock_lookup);
|
||||||
(CMD_EXEC_FATAL_ERROR == status) { return status;
|
if (CMD_EXEC_FATAL_ERROR == status) {
|
||||||
|
return status;
|
||||||
}
|
}
|
||||||
*/
|
|
||||||
|
|
||||||
/* Add GPIO ports from the sub-modules under this Verilog module
|
/* Add GPIO ports from the sub-modules under this Verilog module
|
||||||
* For top-level module, we follow a special sequencing for I/O modules. So we
|
* For top-level module, we follow a special sequencing for I/O modules. So we
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue