From 39543f794517aa50e64c26025e60c33ef1fd9659 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Mon, 1 Feb 2021 10:23:46 -0700
Subject: [PATCH] [HDL] Add carry mux2 to cell library

---
 .../openfpga_cell_library/verilog/mux2.v      | 25 +++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/openfpga_flow/openfpga_cell_library/verilog/mux2.v b/openfpga_flow/openfpga_cell_library/verilog/mux2.v
index 66d204a99..297baedb6 100644
--- a/openfpga_flow/openfpga_cell_library/verilog/mux2.v
+++ b/openfpga_flow/openfpga_cell_library/verilog/mux2.v
@@ -53,3 +53,28 @@ module MUX2(
 `endif
 
 endmodule
+
+//-----------------------------------------------------
+// Design Name : CARRY_MUX2
+// File Name   : mux2.v
+// Function    : Standard cell (static gate) implementation
+//               of 2-input multiplexers to be used by carry logic 
+// Coder       : Xifan Tang
+//-----------------------------------------------------
+
+module CARRY_MUX2(
+    // iVerilog is buggy on the 'input A' declaration when deposit initial
+    // values 
+	input [0:0] A,   // Data input 0
+	input [0:0] B,   // Data input 1
+	input [0:0] S0, // Select port
+	output [0:0] Y  // Data output
+	);
+  
+	assign Y = S0 ? B : A;
+
+// Note: 
+//	 MUX2 appears in the datapath logic driven by carry-in and LUT outputs
+//	 where initial values and signal deposit are not required
+
+endmodule