riscv
/
OpenFPGA
mirror of https://github.com/lnis-uofu/OpenFPGA.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

[test] add a new test case

This commit is contained in:
tangxifan 2024-08-09 17:04:10 -07:00
parent 602ab72002
commit 38f1bdba4e
4 changed files with 69 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
openfpga_flow/regression_test_scripts/basic_reg_test.sh
View File

@ -200,6 +200,7 @@ run-task basic_tests/tile_organization/fabric_tile_global_tile_clock_io_subtile
run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_global_tile_clock $@
run-task basic_tests/tile_organization/fabric_tile_perimeter_cb_pb_pin_fixup $@
run-task basic_tests/tile_organization/fabric_tile_clkntwk_io_subtile $@
run-task basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile $@
run-task basic_tests/tile_organization/homo_fabric_tile_preconfig $@
run-task basic_tests/tile_organization/homo_fabric_tile_2x2_preconfig $@
run-task basic_tests/tile_organization/homo_fabric_tile_4x4_preconfig $@

25
openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile/config/clk_arch_1clk_2layer.xml Normal file
View File

@ -0,0 +1,25 @@
<clock_networks default_segment="L1" default_tap_switch="ipin_cblock" default_driver_switch="0">
<clock_network name="clk_tree_2lvl" global_port="clk[0:0]">
<spine name="spine_lvl0" start_x="0" start_y="1" end_x="2" end_y="1">
<switch_point tap="rib_lvl1_sw0_upper" x="0" y="1"/>
<switch_point tap="rib_lvl1_sw0_lower" x="0" y="1"/>
<switch_point tap="rib_lvl1_sw1_upper" x="1" y="1"/>
<switch_point tap="rib_lvl1_sw1_lower" x="1" y="1"/>
<switch_point tap="rib_lvl1_sw2_upper" x="2" y="1"/>
<switch_point tap="rib_lvl1_sw2_lower" x="2" y="1"/>
</spine>
<spine name="rib_lvl1_sw0_upper" start_x="0" start_y="2" end_x="0" end_y="2" type="CHANY" direction="INC_DIRECTION"/>
<spine name="rib_lvl1_sw0_lower" start_x="0" start_y="1" end_x="0" end_y="1" type="CHANY" direction="DEC_DIRECTION"/>
<spine name="rib_lvl1_sw1_upper" start_x="1" start_y="2" end_x="1" end_y="3" type="CHANY" direction="INC_DIRECTION"/>
<spine name="rib_lvl1_sw1_lower" start_x="1" start_y="1" end_x="1" end_y="0" type="CHANY" direction="DEC_DIRECTION"/>
<spine name="rib_lvl1_sw2_upper" start_x="2" start_y="2" end_x="2" end_y="3" type="CHANY" direction="INC_DIRECTION"/>
<spine name="rib_lvl1_sw2_lower" start_x="2" start_y="1" end_x="2" end_y="0" type="CHANY" direction="DEC_DIRECTION"/>
<taps>
<all from_pin="clk[0:0]" to_pin="clb[0:0].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="io_top[0:5].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="io_right[0:2].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="io_bottom[0:3].clk[0:0]"/>
<all from_pin="clk[0:0]" to_pin="io_left[0:3].clk[0:0]"/>
</taps>
</clock_network>
</clock_networks>

42
openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile/config/task.conf Normal file
View File

@ -0,0 +1,42 @@
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# Configuration file for running experiments
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs
# Each job execute fpga_flow script on combination of architecture & benchmark
# timeout_each_job is timeout for each job
# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
[GENERAL]
run_engine=openfpga_shell
power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml
power_analysis = false
spice_output=false
verilog_output=true
timeout_each_job = 20*60
fpga_flow=yosys_vpr
[OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/group_tile_clkntwk_preconfig_testbench_example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_ClkNtwk_registerable_IoSubtile_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/fixed_sim_openfpga.xml
openfpga_vpr_extra_options=
openfpga_pb_pin_fixup_command=
openfpga_vpr_device=2x2
openfpga_vpr_route_chan_width=40
openfpga_group_tile_config_file=${PATH:TASK_DIR}/config/tile_config.xml
openfpga_verilog_testbench_options=--explicit_port_mapping
openfpga_clock_arch_file=${PATH:TASK_DIR}/config/clk_arch_1clk_2layer.xml
[ARCHITECTURES]
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_PerimeterCb_ClkNtwk_registerable_IoSubtile_40nm.xml
[BENCHMARKS]
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2_pipelined/and2_pipelined.v
[SYNTHESIS_PARAM]
bench_read_verilog_options_common = -nolatches
bench0_top = and2_pipelined
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=

1
openfpga_flow/tasks/basic_tests/tile_organization/fabric_tile_clkntwk_registerable_io_subtile/config/tile_config.xml Normal file
View File

@ -0,0 +1 @@
<tiles style="top_left"/>