diff --git a/.github/PULL_REQUEST_TEMPLATE/pull_request_template.md b/.github/PULL_REQUEST_TEMPLATE/pull_request_template.md
index d1c458c04..8bec074e4 100644
--- a/.github/PULL_REQUEST_TEMPLATE/pull_request_template.md
+++ b/.github/PULL_REQUEST_TEMPLATE/pull_request_template.md
@@ -1,33 +1,35 @@
----
-name: Pull request
-about: Push a change to this project
----
+> ### Motivate of the pull request
+> - [ ] To address an existing issue. If so, please provide a link to the issue: <issue id>
+> - [ ] Breaking new feature. If so, please describe details in the description part.
 
-### Motivate of the pull request
-- [ ] To address an existing issue. If so, please provide a link to the issue.
-- [ ] Breaking new feature. If so, please decribe details in the description part.
+> ### Describe the technical details
+> #### What is currently done? (Provide issue link if applicable)
+> ** Please provide a list of limitations if not specified in any issue **
+> - [ ] <technical details about limitation>
+> - [ ] <more limitations>
+>
+> #### What does this pull request change?
+> ** Please provide a list of highlights of your changes. **
+> - [ ] <details about the technical highlight>
+> - [ ] <more technical highlights>
 
-### Describe the technical details
-- What is currently done? (Provide issue link if applicable)
-- What does this pull request change?
+> ### Which part of the code base require a change
+> **In general, modification on existing submodules are not acceptable. You should push changes to upstream.**
+> - [ ] VPR
+> - [ ] Tileable routing architecture generator
+> - [ ] OpenFPGA libraries
+> - [ ] FPGA-Verilog
+> - [ ] FPGA-Bitstream
+> - [ ] FPGA-SDC
+> - [ ] FPGA-SPICE
+> - [ ] Flow scripts
+> - [ ] Architecture library
+> - [ ] Cell library
+> - [ ] Documentation
+> - [ ] Regression tests
+> - [ ] Continous Integration (CI) scripts
 
-### Which part of the code base require a change
-**In general, modification on existing submodules are not acceptable. You should push changes to upstream.**
-- [ ] VPR
-- [ ] OpenFPGA libraries
-- [ ] FPGA-Verilog
-- [ ] FPGA-Bitstream
-- [ ] FPGA-SDC
-- [ ] FPGA-SPICE
-- [ ] Flow scripts
-- [ ] Architecture library
-- [ ] Cell library
+> ### Impact of the pull request
 
-### Checklist of the pull request
-- [ ] Require code changes. 
-- [ ] Require new tests to be added
-- [ ] Require an update on documentation
-
-### Impact of the pull request
-- [ ] Require a change on Quality of Results (QoR)
-- [ ] Break back-compatibility. If so, please list who may be influenced.
+> - [ ] Require a change on Quality of Results (QoR)
+> - [ ] Break back-compatibility. If so, please list who may be influenced.