From 3811c1895388a0d6d9f463baf58f484903678f20 Mon Sep 17 00:00:00 2001 From: AurelienUoU Date: Thu, 23 May 2019 18:33:47 -0600 Subject: [PATCH] Correct syntax error in tokens of regression_fpga_flow.sh --- fpga_flow/regression_fpga_flow.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga_flow/regression_fpga_flow.sh b/fpga_flow/regression_fpga_flow.sh index 77bf93379..813a8ca8c 100755 --- a/fpga_flow/regression_fpga_flow.sh +++ b/fpga_flow/regression_fpga_flow.sh @@ -17,7 +17,7 @@ cd ${pwd_path}/scripts # SRAM FPGA # TT case -perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -power -remove_designs -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width-vpr_fpga_verilog_include_icarus_simulator -end_flow_with_test +perl fpga_flow.pl -conf ${config_file} -benchmark ${bench_txt} -rpt ${rpt_file} -N 10 -K 6 -ace_d 0.5 -power -remove_designs -multi_thread 1 -vpr_fpga_x2p_rename_illegal_port -vpr_fpga_verilog -vpr_fpga_verilog_dir $verilog_path -vpr_fpga_bitstream_generator -vpr_fpga_verilog_print_autocheck_top_testbench -vpr_fpga_verilog_include_timing -vpr_fpga_verilog_include_signal_init -vpr_fpga_verilog_formal_verification_top_netlist -fix_route_chan_width -vpr_fpga_verilog_include_icarus_simulator -end_flow_with_test rm -rf ${pwd_path}/results rm -rf $verilog_path