From 37d8617a5c35fdda360dbf0d9a674450fd79fc45 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 17 Feb 2022 19:45:37 -0800 Subject: [PATCH] [Doc] Update due to new options --- .../openfpga_commands/fpga_verilog_commands.rst | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst index 9f39f8250..aaebf5f87 100644 --- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst +++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst @@ -120,6 +120,11 @@ write_preconfigured_fabric_wrapper Specify the *Pin Constraints File* (PCF) if you want to custom stimulus in testbenches. For example, ``-pin_constraints_file pin_constraints.xml`` Strongly recommend for multi-clock simulations. See detailed file format about :ref:`file_format_pin_constraints_file`. + .. option:: --bus_group_file or -bgf + + Specify the *Bus Group File* (BGF) if you want to group pins to buses. For example, ``-bgf bus_group.xml`` + Strongly recommend when input HDL contains bus ports. See detailed file format about :ref:`file_format_bus_group_file`. + .. option:: --explicit_port_mapping Use explicit port mapping when writing the Verilog netlists