From 3790f2c26adf3288f3d765373060217fc92f2f72 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Tue, 12 Jan 2021 17:48:52 -0700
Subject: [PATCH] [Benchmark] Add 2-clock micro benchmark

---
 .../counter_2clock/counter_2clock.v           | 29 +++++++++++++
 .../counter_2clock/counter_2clock_tb.v        | 42 +++++++++++++++++++
 2 files changed, 71 insertions(+)
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.v
 create mode 100644 openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock_tb.v

diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.v b/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.v
new file mode 100644
index 000000000..428392581
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock.v
@@ -0,0 +1,29 @@
+module counter_2clock(clk0, q0, rst0, clk1, q1, rst1);
+
+    input clk0;
+    input rst0;
+    output [7:0] q0;
+    reg [7:0] q0;
+
+    input clk1;
+    input rst1;
+    output [7:0] q1;
+    reg [7:0] q1;
+
+    always @ (posedge clk0)
+    begin
+        if(rst0)
+		q0 <= 8'b00000000;
+	else
+		q0 <= q0 + 1;
+    end
+
+    always @ (posedge clk1)
+    begin
+        if(rst1)
+		q1 <= 8'b00000000;
+	else
+		q1 <= q1 + 1;
+    end
+
+endmodule
diff --git a/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock_tb.v b/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock_tb.v
new file mode 100644
index 000000000..d1957dc99
--- /dev/null
+++ b/openfpga_flow/benchmarks/micro_benchmark/counter_2clock/counter_2clock_tb.v
@@ -0,0 +1,42 @@
+module counter_2clock_tb;
+
+	reg clk0, rst0;
+	wire [7:0] q0;
+
+	reg clk1, rst1;
+	wire [7:0] q1;
+
+	counter_2clock C_1(
+		clk0, 
+		q0, 
+		rst0);
+
+	counter_2clock C_1(
+		clk1, 
+		q1, 
+		rst1);
+	
+	initial begin
+		#0 rst0 = 1'b1; clk0 = 1'b0;
+		#100 rst0 = 1'b0;
+	end
+
+	always begin
+		#10 clk0 = ~clk0;
+	end
+
+	initial begin
+		#0 rst1 = 1'b1; clk1 = 1'b0;
+		#100 rst1 = 1'b0;
+	end
+
+	always begin
+		#20 clk1 = ~clk1;
+	end
+
+	
+	initial begin
+		#5000 $stop;
+	end
+
+endmodule