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[Test] Now use pre-configured testbench when verifying signal gen microbenchmarks

This commit is contained in:
tangxifan 2021-10-30 18:03:59 -07:00
parent 7455990ead
commit 370e3fef83
1 changed files with 3 additions and 2 deletions
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5
openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf
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@ -16,7 +16,7 @@ timeout_each_job = 20*60
fpga_flow=yosys_vpr fpga_flow=yosys_vpr
[OpenFPGA_SHELL] [OpenFPGA_SHELL]
openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga
openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml
openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml
openfpga_vpr_device_layout= openfpga_vpr_device_layout=
@ -41,4 +41,5 @@ bench2_top = reset_generator
bench2_chan_width = 300 bench2_chan_width = 300
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test= #end_flow_with_test=
vpr_fpga_verilog_formal_verification_top_netlist=