From 370e3fef836954fba5662313a0579111aba44454 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 30 Oct 2021 18:03:59 -0700 Subject: [PATCH] [Test] Now use pre-configured testbench when verifying signal gen microbenchmarks --- .../tasks/benchmark_sweep/signal_gen/config/task.conf | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf index 9ada9e960..a6825d862 100644 --- a/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf +++ b/openfpga_flow/tasks/benchmark_sweep/signal_gen/config/task.conf @@ -16,7 +16,7 @@ timeout_each_job = 20*60 fpga_flow=yosys_vpr [OpenFPGA_SHELL] -openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/write_full_testbench_example_script.openfpga +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/example_script.openfpga openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_cc_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout= @@ -41,4 +41,5 @@ bench2_top = reset_generator bench2_chan_width = 300 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] -end_flow_with_test= +#end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist=