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[Script] Support simplified rewriting for Yosys on output verilog

This commit is contained in:
tangxifan 2022-02-18 14:54:39 -08:00
parent 401f673f16
commit 36543f7f2f
2 changed files with 2 additions and 1 deletions
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1
openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
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@ -39,3 +39,4 @@ synth -run check
# Clean and output blif
opt_clean -purge
write_blif rewritten_${OUTPUT_BLIF}
write_verilog ${OUTPUT_VERILOG}

2
openfpga_flow/tasks/basic_tests/bus_group/preconfig_testbench_explicit_mapping/config/task.conf
View File

@ -38,7 +38,7 @@ bench_yosys_dsp_map_verilog_common=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_
bench_yosys_dsp_map_parameters_common=-D DSP_A_MAXWIDTH=36 -D DSP_B_MAXWIDTH=36 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_NAME=mult_36x36
bench_read_verilog_options_common = -nolatches
bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys;${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_rewrite_flow.ys
bench_yosys_rewrite_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_flow_with_rewrite.ys
bench0_top = counter
bench0_openfpga_pin_constraints_file=${PATH:TASK_DIR}/config/pin_constraints_reset.xml