diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml
index 095a82096..038161627 100644
--- a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml
+++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml
@@ -136,7 +136,7 @@
         <output name="d_out" num_pins="8"/>
         <clock name="clk" num_pins="1"/>
         <fc in_type="frac" in_val="0.25" out_type="frac" out_val="0.20"/>
-        <pinlocations pattern="spread"/>
+        <pinlocations pattern="perimeter"/>
       </sub_tile>
     </tile>
   </tiles>