Merge branch 'dev' into documentation
This commit is contained in:
AurelienUoU
commit
35e1962732
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@ -46,7 +46,8 @@ my @supported_flows = ("standard",
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"mpack1",
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"vtr",
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"vtr_standard",
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"yosys_vpr");
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"yosys_vpr",
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"vpr_only");
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my %selected_flows;
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# Configuration file keywords list
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@ -761,6 +762,8 @@ sub run_abc_fpgamap($ $ $)
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# Run ABC by FPGA-oriented synthesis
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sub run_abc_bb_fpgamap($ $ $) {
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my ($bm,$blif_out,$log) = @_;
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my ($cmd_log) = ($log."cmd");
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# Get ABC path
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my ($abc_dir,$abc_name) = &split_prog_path($conf_ptr->{dir_path}->{abc_with_bb_support_path}->{val});
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my ($lut_num) = $opt_ptr->{K_val};
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@ -777,9 +780,26 @@ sub run_abc_bb_fpgamap($ $ $) {
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$dump_verilog = "write_verilog $bm.v";
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}
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#
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# Create a local copy for the commands
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#
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my ($ABC_CMD_FH) = (FileHandle->new);
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if ($ABC_CMD_FH->open("> $cmd_log")) {
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print "INFO: auto generating cmds for ABC ($cmd_log) ...\n";
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} else {
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die "ERROR: fail to auto generating cmds for ABC ($cmd_log) ...\n";
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}
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# Output the standard format (refer to VTR_flow script)
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print $ABC_CMD_FH "read $bm; resyn; resyn2; $fpga_synthesis_method -K $lut_num; $abc_seq_optimize sweep; write_hie $bm $blif_out; $dump_verilog; quit;\n";
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close($ABC_CMD_FH);
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# Go to ABC directory and run FPGA with commands
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print "Entering $abc_dir\n";
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chdir $abc_dir;
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# Run FPGA ABC
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system("./$abc_name -c \"read $bm; resyn; resyn2; $fpga_synthesis_method -K $lut_num; $abc_seq_optimize sweep; write_hie $bm $blif_out; $dump_verilog; quit;\" > $log");
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system("./$abc_name -F $cmd_log > $log");
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if (!(-e $blif_out)) {
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die "ERROR: Fail ABC_with_bb_support for benchmark $bm.\n";
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@ -789,6 +809,7 @@ sub run_abc_bb_fpgamap($ $ $) {
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die "ERROR: ABC verilog rewrite failed for benchmark $bm!\n";
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}
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print "Leaving $abc_dir\n";
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chdir $cwd;
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}
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@ -2004,6 +2025,34 @@ sub parse_yosys_vpr_flow_results($ $ $ $)
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return;
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}
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sub run_vpr_only_flow($ $ $ $ $)
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{
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my ($tag,$benchmark_file,$vpr_arch, $parse_results) = @_;
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my ($benchmark, $rpt_dir,$prefix);
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my ($vpr_net,$vpr_place,$vpr_route,$vpr_reroute_log,$vpr_log);
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$benchmark = $benchmark_file;
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$benchmark =~ s/\.blif$//g;
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# Run Standard flow
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$rpt_dir = "$conf_ptr->{dir_path}->{rpt_dir}->{val}"."/$benchmark/$tag";
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&generate_path($rpt_dir);
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$prefix = "$rpt_dir/$benchmark\_"."K$opt_ptr->{K_val}\_"."N$opt_ptr->{N_val}\_";
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my ($input_blif) = ("$conf_ptr->{dir_path}->{benchmark_dir}->{val}"."/$benchmark".".blif");
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my ($act_file,$ace_new_blif,$ace_log) = ("$prefix"."ace.act","$prefix"."ace.blif","$prefix"."ace.log");
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$vpr_net = "$prefix"."vpr.net";
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$vpr_place = "$prefix"."vpr.place";
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$vpr_route = "$prefix"."vpr.route";
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$vpr_log = "$prefix"."vpr.log";
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$vpr_reroute_log = "$prefix"."vpr_reroute.log";
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&run_ace_in_flow($prefix, $input_blif, $act_file, $ace_new_blif, $ace_log);
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&run_vpr_in_flow($tag, $benchmark, $benchmark_file, $input_blif, $vpr_arch, $act_file, $vpr_net, $vpr_place, $vpr_route, $vpr_log, $vpr_reroute_log, $parse_results);
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return;
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}
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sub run_standard_flow($ $ $ $ $)
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{
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@ -2728,6 +2777,8 @@ sub run_benchmark_selected_flow($ $ $)
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&run_mig_mccl_flow("mig_mccl",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, $parse_results);
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} elsif ($flow_type eq "yosys_vpr") {
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&run_yosys_vpr_flow("yosys_vpr",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, "classic", $parse_results);
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} elsif ($flow_type eq "vpr_only") {
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&run_vpr_only_flow("vpr_only",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, $parse_results);
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} else {
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die "ERROR: unsupported flow type ($flow_type) is chosen!\n";
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}
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@ -2756,6 +2807,8 @@ sub parse_benchmark_selected_flow($ $) {
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&parse_standard_flow_results("mig_mccl", $benchmark, $conf_ptr->{flow_conf}->{vpr_arch}->{val}, "abc_black_box");
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} elsif ($flow_type eq "yosys_vpr") {
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&parse_yosys_vpr_flow_results("yosys_vpr",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val},"abc_black_box");
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} elsif ($flow_type eq "vpr_only") {
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&parse_standard_flow_results("vpr_only",$benchmark,$conf_ptr->{flow_conf}->{vpr_arch}->{val}, "classic");
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} else {
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die "ERROR: unsupported flow type ($flow_type) is chosen!\n";
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}
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@ -3547,6 +3600,11 @@ sub gen_csv_rpt($)
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print "INFO: writing yosys_vpr flow results ...\n";
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&gen_csv_rpt_yosys_vpr_flow("yosys_vpr",$CSVFH);
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}
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} elsif ($flow_type eq "vpr_only") {
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if (1 == &check_flow_all_benchmarks_done("vpr_only")) {
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print "INFO: writing vpr_only flow results ...\n";
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&gen_csv_rpt_standard_flow("vpr_only",$CSVFH);
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}
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} else {
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die "ERROR: flow_type: $flow_type is not supported!\n";
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}
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@ -147,6 +147,7 @@ sub process_blifmodel($ $) {
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if ($temp eq $default_clk_name) {
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$have_default_clk = 1;
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$clk_num++;
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print "Found 1 clock: $temp in @tokens\n";
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last;
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}
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}
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@ -244,7 +244,7 @@ void load_one_grid_rr_nodes_basic_info(const DeviceCoordinator& grid_coordinator
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rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x();
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rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x();
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rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y();
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rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y();
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rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y() + cur_grid.type->height - 1;
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rr_graph->rr_node[*cur_node_id].ptc_num = opin_list[pin];
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rr_graph->rr_node[*cur_node_id].capacity = 1;
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rr_graph->rr_node[*cur_node_id].occ = 0;
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@ -253,6 +253,15 @@ void load_one_grid_rr_nodes_basic_info(const DeviceCoordinator& grid_coordinator
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/* Switch info */
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rr_graph->rr_node[*cur_node_id].driver_switch = delayless_switch;
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/* fill fast look-up table */
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/* If height > 1, we will update fast lookup to twice:
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* 1. for the x, y + height. This enable fast fast look-up for node collection in rr_gsb
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* 2. for the x, y. This enables fast lookup for SOURCE and SINK nodes drive/driven by the node
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*/
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load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id,
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rr_graph->rr_node[*cur_node_id].type,
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rr_graph->rr_node[*cur_node_id].xlow,
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rr_graph->rr_node[*cur_node_id].ylow + height,
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rr_graph->rr_node[*cur_node_id].ptc_num);
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load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id,
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rr_graph->rr_node[*cur_node_id].type,
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rr_graph->rr_node[*cur_node_id].xlow,
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@ -269,7 +278,7 @@ void load_one_grid_rr_nodes_basic_info(const DeviceCoordinator& grid_coordinator
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rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x();
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rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x();
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rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y();
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rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y();
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rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y() + cur_grid.type->height - 1;
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rr_graph->rr_node[*cur_node_id].ptc_num = ipin_list[pin];
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rr_graph->rr_node[*cur_node_id].capacity = 1;
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rr_graph->rr_node[*cur_node_id].occ = 0;
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@ -278,6 +287,15 @@ void load_one_grid_rr_nodes_basic_info(const DeviceCoordinator& grid_coordinator
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/* Switch info */
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rr_graph->rr_node[*cur_node_id].driver_switch = wire_to_ipin_switch;
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/* fill fast look-up table */
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/* If height > 1, we will update fast lookup to twice:
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* 1. for the x, y + height. This enable fast fast look-up for node collection in rr_gsb
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* 2. for the x, y. This enables fast lookup for SOURCE and SINK nodes drive/driven by the node
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*/
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load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id,
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rr_graph->rr_node[*cur_node_id].type,
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rr_graph->rr_node[*cur_node_id].xlow,
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rr_graph->rr_node[*cur_node_id].ylow + height,
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rr_graph->rr_node[*cur_node_id].ptc_num);
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load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id,
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rr_graph->rr_node[*cur_node_id].type,
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rr_graph->rr_node[*cur_node_id].xlow,
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@ -289,46 +307,44 @@ void load_one_grid_rr_nodes_basic_info(const DeviceCoordinator& grid_coordinator
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} /* End of side enumeration */
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} /* End of height enumeration */
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/* Walk through the height of each grid,
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/* No need to Walk through the height of each grid,
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* get pins and configure the rr_nodes */
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for (int height = 0; height < cur_grid.type->height; ++height) {
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/* Set a SOURCE or a SINK rr_node for each class */
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for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) {
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/* Set a SINK rr_node for the OPIN */
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if ( DRIVER == cur_grid.type->class_inf[iclass].type) {
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rr_graph->rr_node[*cur_node_id].type = SOURCE;
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}
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if ( RECEIVER == cur_grid.type->class_inf[iclass].type) {
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rr_graph->rr_node[*cur_node_id].type = SINK;
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}
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rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x();
|
||||
rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x();
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rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y();
|
||||
rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y();
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rr_graph->rr_node[*cur_node_id].ptc_num = iclass;
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/* FIXME: need to confirm if the capacity should be the number of pins in this class*/
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rr_graph->rr_node[*cur_node_id].capacity = cur_grid.type->class_inf[iclass].num_pins;
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rr_graph->rr_node[*cur_node_id].occ = 0;
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/* cost index is a FIXED value for SOURCE and SINK */
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if (SOURCE == rr_graph->rr_node[*cur_node_id].type) {
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rr_graph->rr_node[*cur_node_id].cost_index = SOURCE_COST_INDEX;
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}
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if (SINK == rr_graph->rr_node[*cur_node_id].type) {
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rr_graph->rr_node[*cur_node_id].cost_index = SINK_COST_INDEX;
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}
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/* Switch info */
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rr_graph->rr_node[*cur_node_id].driver_switch = delayless_switch;
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/* TODO: should we set pb_graph_pin here? */
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/* fill fast look-up table */
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load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id,
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rr_graph->rr_node[*cur_node_id].type,
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rr_graph->rr_node[*cur_node_id].xlow,
|
||||
rr_graph->rr_node[*cur_node_id].ylow,
|
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rr_graph->rr_node[*cur_node_id].ptc_num);
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/* Update node counter */
|
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(*cur_node_id)++;
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} /* End of height enumeration */
|
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} /* End of pin_class enumeration */
|
||||
/* Set a SOURCE or a SINK rr_node for each class */
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for (int iclass = 0; iclass < cur_grid.type->num_class; ++iclass) {
|
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/* Set a SINK rr_node for the OPIN */
|
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if ( DRIVER == cur_grid.type->class_inf[iclass].type) {
|
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rr_graph->rr_node[*cur_node_id].type = SOURCE;
|
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}
|
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if ( RECEIVER == cur_grid.type->class_inf[iclass].type) {
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rr_graph->rr_node[*cur_node_id].type = SINK;
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}
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rr_graph->rr_node[*cur_node_id].xlow = grid_coordinator.get_x();
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rr_graph->rr_node[*cur_node_id].xhigh = grid_coordinator.get_x();
|
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rr_graph->rr_node[*cur_node_id].ylow = grid_coordinator.get_y();
|
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rr_graph->rr_node[*cur_node_id].yhigh = grid_coordinator.get_y() + cur_grid.type->height - 1;
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rr_graph->rr_node[*cur_node_id].ptc_num = iclass;
|
||||
/* FIXME: need to confirm if the capacity should be the number of pins in this class*/
|
||||
rr_graph->rr_node[*cur_node_id].capacity = cur_grid.type->class_inf[iclass].num_pins;
|
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rr_graph->rr_node[*cur_node_id].occ = 0;
|
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/* cost index is a FIXED value for SOURCE and SINK */
|
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if (SOURCE == rr_graph->rr_node[*cur_node_id].type) {
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rr_graph->rr_node[*cur_node_id].cost_index = SOURCE_COST_INDEX;
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}
|
||||
if (SINK == rr_graph->rr_node[*cur_node_id].type) {
|
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rr_graph->rr_node[*cur_node_id].cost_index = SINK_COST_INDEX;
|
||||
}
|
||||
/* Switch info */
|
||||
rr_graph->rr_node[*cur_node_id].driver_switch = delayless_switch;
|
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/* TODO: should we set pb_graph_pin here? */
|
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/* fill fast look-up table */
|
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load_one_node_to_rr_graph_fast_lookup(rr_graph, *cur_node_id,
|
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rr_graph->rr_node[*cur_node_id].type,
|
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rr_graph->rr_node[*cur_node_id].xlow,
|
||||
rr_graph->rr_node[*cur_node_id].ylow,
|
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rr_graph->rr_node[*cur_node_id].ptc_num);
|
||||
/* Update node counter */
|
||||
(*cur_node_id)++;
|
||||
} /* End of height enumeration */
|
||||
|
||||
return;
|
||||
}
|
||||
|
|
@ -640,7 +656,7 @@ void load_rr_nodes_basic_info(t_rr_graph* rr_graph,
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|| (OPIN == rr_graph->rr_node[inode].type)
|
||||
|| (IPIN == rr_graph->rr_node[inode].type));
|
||||
assert (rr_graph->rr_node[inode].xlow == rr_graph->rr_node[inode].xhigh);
|
||||
assert (rr_graph->rr_node[inode].ylow == rr_graph->rr_node[inode].yhigh);
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||||
assert (rr_graph->rr_node[inode].ylow + grids[rr_graph->rr_node[inode].xlow][rr_graph->rr_node[inode].ylow].type->height - 1 == rr_graph->rr_node[inode].yhigh);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -993,6 +1009,13 @@ void build_tileable_unidir_rr_graph(INP const int L_num_types,
|
|||
***********************************************************************/
|
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alloc_rr_graph_fast_lookup(device_size, &rr_graph);
|
||||
|
||||
/* FIXME: DEBUG CODES TO BE REMOVED
|
||||
vpr_printf(TIO_MESSAGE_INFO, "estimated %lu SOURCE NODE.\n", num_rr_nodes_per_type[SOURCE]);
|
||||
vpr_printf(TIO_MESSAGE_INFO, "estimated %lu SINK NODE.\n", num_rr_nodes_per_type[SINK]);
|
||||
vpr_printf(TIO_MESSAGE_INFO, "estimated %lu OPIN NODE.\n", num_rr_nodes_per_type[OPIN]);
|
||||
vpr_printf(TIO_MESSAGE_INFO, "estimated %lu IPIN NODE.\n", num_rr_nodes_per_type[IPIN]);
|
||||
*/
|
||||
|
||||
load_rr_nodes_basic_info(&rr_graph, device_size, grids, device_chan_width, segment_infs,
|
||||
wire_to_ipin_switch, delayless_switch);
|
||||
|
||||
|
|
|
|||
|
|
@ -736,7 +736,7 @@ t_block* search_mapped_block(int x, int y, int z) {
|
|||
assert((0 < x)||(0 == x));
|
||||
assert((x < (nx + 1))||(x == (nx + 1)));
|
||||
assert((0 < y)||(0 == y));
|
||||
assert((x < (ny + 1))||(x == (ny + 1)));
|
||||
assert((y < (ny + 1))||(y == (ny + 1)));
|
||||
|
||||
/* Search all blocks*/
|
||||
for (iblk = 0; iblk < num_blocks; iblk++) {
|
||||
|
|
@ -3479,10 +3479,10 @@ int my_strlen_int(int input_int) {
|
|||
|
||||
boolean my_bool_to_boolean(bool my_bool) {
|
||||
|
||||
if(true == my_bool)
|
||||
if(true == my_bool) {
|
||||
return TRUE;
|
||||
if(false == my_bool)
|
||||
return FALSE;
|
||||
vpr_printf(TIO_MESSAGE_ERROR,"Failure to convert bool to boolean. Parameter is neither true nor false.\n");
|
||||
exit(1);
|
||||
} else {
|
||||
assert (false == my_bool);
|
||||
return FALSE;
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -373,7 +373,9 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
|
|||
fprintf(fp, ".%s(",
|
||||
pb_type_port->spice_model_port->lib_name);
|
||||
}
|
||||
fprintf(fp, "{");
|
||||
if (1 < pb_type_port->num_pins) {
|
||||
fprintf(fp, "{");
|
||||
}
|
||||
for (int ipin = 0; ipin < pb_type_port->num_pins; ++ipin) {
|
||||
if (0 < ipin) {
|
||||
fprintf(fp, ", ");
|
||||
|
|
@ -381,7 +383,9 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
|
|||
fprintf(fp, "%s",
|
||||
gen_verilog_one_pb_type_pin_name(port_prefix, pb_type_port, ipin));
|
||||
}
|
||||
fprintf(fp, "}");
|
||||
if (1 < pb_type_port->num_pins) {
|
||||
fprintf(fp, "}");
|
||||
}
|
||||
if (TRUE == dump_explicit_port_map) {
|
||||
fprintf(fp, ")");
|
||||
}
|
||||
|
|
|
|||
|
|
@ -134,7 +134,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
|
|||
get_sram_orgz_info_num_blwl(cur_sram_orgz_info, &cur_bl, &cur_wl);
|
||||
|
||||
/* print ports --> input ports */
|
||||
dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, TRUE, FALSE, FALSE, false);
|
||||
dump_verilog_pb_type_ports(fp, port_prefix, 0, prim_pb_type, TRUE, FALSE, FALSE, true);
|
||||
/* IOPADs requires a specical port to output */
|
||||
if (SPICE_MODEL_IOPAD == verilog_model->type) {
|
||||
fprintf(fp, ",\n");
|
||||
|
|
@ -222,34 +222,41 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
|
|||
fprintf(fp, "`endif\n");
|
||||
}
|
||||
|
||||
/* Explicit port map support: turn it on when there is need for the full netlist or just standard cell */
|
||||
boolean subckt_require_explicit_port_map = FALSE;
|
||||
if ( (TRUE == verilog_model->dump_explicit_port_map) || (true == is_explicit_mapping) ) {
|
||||
subckt_require_explicit_port_map = TRUE;
|
||||
}
|
||||
|
||||
/* Call the subckt*/
|
||||
fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt);
|
||||
fprintf(fp, "\n");
|
||||
/* Only dump the global ports belonging to a spice_model
|
||||
* Disable recursive here !
|
||||
*/
|
||||
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
|
||||
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) {
|
||||
fprintf(fp, ",\n");
|
||||
}
|
||||
|
||||
/* assert */
|
||||
num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1);
|
||||
/* print ports --> input ports */
|
||||
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping));
|
||||
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE,
|
||||
subckt_require_explicit_port_map);
|
||||
/* IOPADs requires a specical port to output */
|
||||
if (SPICE_MODEL_IOPAD == verilog_model->type) {
|
||||
fprintf(fp, ",\n");
|
||||
assert(1 == num_pad_port);
|
||||
assert(NULL != pad_ports[0]);
|
||||
/* Add explicit port mapping if required */
|
||||
if (true == is_explicit_mapping) {
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ".%s(",
|
||||
pad_ports[0]->lib_name);
|
||||
}
|
||||
/* Print inout port */
|
||||
fprintf(fp, "%s%s[%d]", gio_inout_prefix,
|
||||
verilog_model->prefix, verilog_model->cnt);
|
||||
if (true == is_explicit_mapping) {
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ")");
|
||||
}
|
||||
fprintf(fp, ", ");
|
||||
|
|
@ -263,7 +270,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
|
|||
case SPICE_SRAM_SCAN_CHAIN:
|
||||
/* Add explicit port mapping if required */
|
||||
if ( (0 < num_sram)
|
||||
&& (true == is_explicit_mapping)) {
|
||||
&& (TRUE == subckt_require_explicit_port_map)) {
|
||||
assert( 1 == num_sram_port);
|
||||
assert( NULL != sram_ports[0]);
|
||||
fprintf(fp, ".%s(",
|
||||
|
|
@ -273,7 +280,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
|
|||
cur_num_sram, cur_num_sram + num_sram - 1,
|
||||
0, VERILOG_PORT_CONKT);
|
||||
if ( (0 < num_sram)
|
||||
&& (true == is_explicit_mapping)) {
|
||||
&& (true == subckt_require_explicit_port_map)) {
|
||||
fprintf(fp, ")");
|
||||
}
|
||||
|
||||
|
|
@ -284,7 +291,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
|
|||
fprintf(fp, ", ");
|
||||
/* Add explicit port mapping if required */
|
||||
if ( (0 < num_sram)
|
||||
&& (true == is_explicit_mapping)) {
|
||||
&& (TRUE == subckt_require_explicit_port_map)) {
|
||||
assert( 1 == num_sram_port);
|
||||
assert( NULL != sram_ports[0]);
|
||||
fprintf(fp, ".%s(",
|
||||
|
|
@ -294,14 +301,14 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
|
|||
cur_num_sram, cur_num_sram + num_sram - 1,
|
||||
1, VERILOG_PORT_CONKT);
|
||||
if ( (0 < num_sram)
|
||||
&& (true == is_explicit_mapping)) {
|
||||
&& (TRUE == verilog_model->dump_explicit_port_map || is_explicit_mapping)) {
|
||||
fprintf(fp, ")");
|
||||
}
|
||||
break;
|
||||
case SPICE_SRAM_MEMORY_BANK:
|
||||
/* Add explicit port mapping if required */
|
||||
if ( (0 < num_sram)
|
||||
&& (true == is_explicit_mapping)) {
|
||||
&& (TRUE == subckt_require_explicit_port_map)) {
|
||||
assert( 1 == num_sram_port);
|
||||
assert( NULL != sram_ports[0]);
|
||||
fprintf(fp, ".%s(",
|
||||
|
|
@ -311,7 +318,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
|
|||
cur_num_sram, cur_num_sram + num_sram - 1,
|
||||
0, VERILOG_PORT_CONKT);
|
||||
if ( (0 < num_sram)
|
||||
&& (true == is_explicit_mapping)) {
|
||||
&& (TRUE == subckt_require_explicit_port_map)) {
|
||||
fprintf(fp, ")");
|
||||
}
|
||||
/* Check if we have an inverterd prefix */
|
||||
|
|
@ -321,7 +328,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
|
|||
fprintf(fp, ", ");
|
||||
/* Add explicit port mapping if required */
|
||||
if ( (0 < num_sram)
|
||||
&& (true == is_explicit_mapping)) {
|
||||
&& (TRUE == subckt_require_explicit_port_map)) {
|
||||
assert( 1 == num_sram_port);
|
||||
assert( NULL != sram_ports[0]);
|
||||
fprintf(fp, ".%s(",
|
||||
|
|
@ -331,7 +338,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
|
|||
cur_num_sram, cur_num_sram + num_sram - 1,
|
||||
1, VERILOG_PORT_CONKT);
|
||||
if ( (0 < num_sram)
|
||||
&& (true == is_explicit_mapping)) {
|
||||
&& (TRUE == subckt_require_explicit_port_map)) {
|
||||
fprintf(fp, ")");
|
||||
}
|
||||
break;
|
||||
|
|
@ -594,6 +601,11 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
|
|||
num_sram = count_num_sram_bits_one_spice_model(verilog_model, -1);
|
||||
cur_num_sram = get_sram_orgz_info_num_mem_bit(cur_sram_orgz_info);
|
||||
|
||||
/* Explicit port map support: turn it on when there is need for the full netlist or just standard cell */
|
||||
boolean subckt_require_explicit_port_map = FALSE;
|
||||
if ( (TRUE == verilog_model->dump_explicit_port_map) || (true == is_explicit_mapping) ) {
|
||||
subckt_require_explicit_port_map = TRUE;
|
||||
}
|
||||
/* Call LUT subckt*/
|
||||
fprintf(fp, "%s %s_%d_ (", verilog_model->name, verilog_model->prefix, verilog_model->cnt);
|
||||
fprintf(fp, "\n");
|
||||
|
|
@ -602,13 +614,13 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
|
|||
* Only dump the global ports belonging to a spice_model
|
||||
* DISABLE recursive here !
|
||||
*/
|
||||
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
|
||||
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) {
|
||||
fprintf(fp, ",\n");
|
||||
}
|
||||
/* Connect inputs*/
|
||||
/* Connect outputs*/
|
||||
fprintf(fp, "//----- Input and output ports -----\n");
|
||||
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, cur_pb_type, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping));
|
||||
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, cur_pb_type, FALSE, TRUE, subckt_require_explicit_port_map);
|
||||
fprintf(fp, "\n//----- SRAM ports -----\n");
|
||||
|
||||
/* check */
|
||||
|
|
@ -620,88 +632,88 @@ void dump_verilog_pb_primitive_lut(t_sram_orgz_info* cur_sram_orgz_info,
|
|||
case SPICE_SRAM_STANDALONE:
|
||||
break;
|
||||
case SPICE_SRAM_SCAN_CHAIN:
|
||||
if (true == is_explicit_mapping) {
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ".sram_out( ");
|
||||
}
|
||||
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
|
||||
cur_num_sram, cur_num_sram + num_lut_sram - 1,
|
||||
0, VERILOG_PORT_CONKT);
|
||||
if (true == is_explicit_mapping) {
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ")");
|
||||
}
|
||||
fprintf(fp, ", ");
|
||||
if (true == is_explicit_mapping) {
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ".sram_outb( ");
|
||||
}
|
||||
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
|
||||
cur_num_sram, cur_num_sram + num_lut_sram - 1,
|
||||
1, VERILOG_PORT_CONKT);
|
||||
if (true == is_explicit_mapping) {
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ")");
|
||||
}
|
||||
if (0 < num_mode_sram) {
|
||||
fprintf(fp, ", ");
|
||||
if (true == is_explicit_mapping) {
|
||||
}
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ".mode_out( ");
|
||||
}
|
||||
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
|
||||
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
|
||||
0, VERILOG_PORT_CONKT);
|
||||
if (true == is_explicit_mapping) {
|
||||
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
|
||||
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
|
||||
0, VERILOG_PORT_CONKT);
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ")");
|
||||
}
|
||||
fprintf(fp, ", ");
|
||||
if (true == is_explicit_mapping) {
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ".mode_outb( ");
|
||||
}
|
||||
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
|
||||
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
|
||||
1, VERILOG_PORT_CONKT);
|
||||
if (true == is_explicit_mapping) {
|
||||
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
|
||||
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
|
||||
1, VERILOG_PORT_CONKT);
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ")");
|
||||
}
|
||||
}
|
||||
break;
|
||||
case SPICE_SRAM_MEMORY_BANK:
|
||||
if (true == is_explicit_mapping) {
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ".sram_out( ");
|
||||
}
|
||||
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
|
||||
cur_num_sram, cur_num_sram + num_lut_sram - 1,
|
||||
0, VERILOG_PORT_CONKT);
|
||||
if (true == is_explicit_mapping) {
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ")");
|
||||
}
|
||||
fprintf(fp, ", ");
|
||||
if (true == is_explicit_mapping) {
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ".sram_outb( ");
|
||||
}
|
||||
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
|
||||
cur_num_sram, cur_num_sram + num_lut_sram - 1,
|
||||
1, VERILOG_PORT_CONKT);
|
||||
if (true == is_explicit_mapping) {
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ")");
|
||||
}
|
||||
if (0 < num_mode_sram) {
|
||||
fprintf(fp, ", ");
|
||||
if (true == is_explicit_mapping) {
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ".mode_out( ");
|
||||
}
|
||||
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
|
||||
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
|
||||
0, VERILOG_PORT_CONKT);
|
||||
if (true == is_explicit_mapping) {
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ")");
|
||||
}
|
||||
fprintf(fp, ", ");
|
||||
if (true == is_explicit_mapping) {
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ".mode_outb( ");
|
||||
}
|
||||
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
|
||||
cur_num_sram + num_lut_sram, cur_num_sram + num_lut_sram + num_mode_sram - 1,
|
||||
1, VERILOG_PORT_CONKT);
|
||||
}
|
||||
if (true == is_explicit_mapping) {
|
||||
if (TRUE == subckt_require_explicit_port_map) {
|
||||
fprintf(fp, ")");
|
||||
}
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -667,10 +667,12 @@ void verilog_generate_sdc_constrain_one_cb_path(FILE* fp,
|
|||
}
|
||||
|
||||
/* Check */
|
||||
assert ((INC_DIRECTION == src_rr_node->direction)
|
||||
||(DEC_DIRECTION == src_rr_node->direction));
|
||||
if (! ((CHANX == src_rr_node->type) ||(CHANY == src_rr_node->type)))
|
||||
assert ((CHANX == src_rr_node->type)
|
||||
||(CHANY == src_rr_node->type));
|
||||
|
||||
assert ((INC_DIRECTION == src_rr_node->direction)
|
||||
||(DEC_DIRECTION == src_rr_node->direction));
|
||||
assert (IPIN == des_rr_node->type);
|
||||
|
||||
fprintf(fp, "set_max_delay");
|
||||
|
|
@ -928,6 +930,13 @@ void verilog_generate_sdc_constrain_one_cb(FILE* fp,
|
|||
for (size_t inode = 0; inode < rr_gsb.get_num_ipin_nodes(cb_ipin_side); ++inode) {
|
||||
t_rr_node* cur_ipin_node = rr_gsb.get_ipin_node(cb_ipin_side, inode);
|
||||
for (int iedge = 0; iedge < cur_ipin_node->num_drive_rr_nodes; iedge++) {
|
||||
/* Skip the drivers that are not CHANX or CHANY.
|
||||
* OPINs should be handled by directlist
|
||||
*/
|
||||
if ( (CHANX != cur_ipin_node->drive_rr_nodes[iedge]->type)
|
||||
&& (CHANY != cur_ipin_node->drive_rr_nodes[iedge]->type) ) {
|
||||
continue;
|
||||
}
|
||||
/* Get the switch delay */
|
||||
int switch_id = cur_ipin_node->drive_switches[iedge];
|
||||
float switch_delay = get_switch_sdc_tmax (&(switch_inf[switch_id]));
|
||||
|
|
|
|||
|
|
@ -902,8 +902,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp,
|
|||
/* Add explicit port mapping if required */
|
||||
if (TRUE == require_explicit_port_map ) {
|
||||
fprintf(fp, ".%s(",
|
||||
/* cur_spice_model_port->lib_name); /* Old version*/
|
||||
cur_spice_model_port->prefix);
|
||||
cur_spice_model_port->lib_name);
|
||||
/*cur_spice_model_port->prefix);*/
|
||||
}
|
||||
fprintf(fp, "%s[0:%d]",
|
||||
cur_spice_model_port->prefix,
|
||||
|
|
|
|||
Loading…
Reference in New Issue