From 35d47ee0e74a656d3c712a8052cf28d6b962d07e Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 16 Sep 2020 17:33:54 -0600 Subject: [PATCH] [Regression tests] bug fix in the test case for fully connected output crossbar --- .../fully_connected_output_crossbar/config/task.conf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/openfpga_flow/tasks/fpga_verilog/fully_connected_output_crossbar/config/task.conf b/openfpga_flow/tasks/fpga_verilog/fully_connected_output_crossbar/config/task.conf index e9e253d1d..f8717b5fd 100644 --- a/openfpga_flow/tasks/fpga_verilog/fully_connected_output_crossbar/config/task.conf +++ b/openfpga_flow/tasks/fpga_verilog/fully_connected_output_crossbar/config/task.conf @@ -17,12 +17,12 @@ fpga_flow=vpr_blif [OpenFPGA_SHELL] openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/OpenFPGAShellScripts/example_script.openfpga -openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_frame_40nm_openfpga.xml +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_N4_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml external_fabric_key_file= [ARCHITECTURES] -arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_N4_tileable_full_output_crossbar_40nm.xml +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_N4_tileable_full_output_crossbar_40nm.xml [BENCHMARKS] bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif