From 35073f48cf9e16be1e593befa11a1dfa5ff4ea48 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sun, 27 Oct 2019 19:10:21 -0600 Subject: [PATCH] add runtime profiling to module graph builders --- .../module_builder/build_decoder_modules.cpp | 15 +++++++++ .../build_essential_modules.cpp | 31 +++++++++++++++++-- .../module_builder/build_grid_modules.cpp | 15 +++++++++ .../module_builder/build_lut_modules.cpp | 14 +++++++++ .../module_builder/build_memory_modules.cpp | 14 +++++++++ .../module_builder/build_mux_modules.cpp | 14 +++++++++ .../module_builder/build_routing_modules.cpp | 28 +++++++++++++++++ .../module_builder/build_top_module.cpp | 15 +++++++++ .../module_builder/build_wire_modules.cpp | 15 +++++++++ 9 files changed, 159 insertions(+), 2 deletions(-) diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.cpp index e8b02998e..ff9999f64 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_decoder_modules.cpp @@ -4,6 +4,7 @@ * 2. Decoders used by grid/routing/top-level module for memory address decoding ***************************************************************************************/ #include +#include #include "util.h" #include "vtr_assert.h" @@ -93,6 +94,12 @@ void build_mux_local_decoder_module(ModuleManager& module_manager, void build_mux_local_decoder_modules(ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building local encoder (for multiplexers) modules..."); + /* Create a library for local encoders with different sizes */ DecoderLibrary decoder_lib; @@ -128,4 +135,12 @@ void build_mux_local_decoder_modules(ModuleManager& module_manager, for (const auto& decoder : decoder_lib.decoders()) { build_mux_local_decoder_module(module_manager, decoder_lib, decoder); } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp index 3145017c3..a474ab26c 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_essential_modules.cpp @@ -148,6 +148,11 @@ void build_gate_module(ModuleManager& module_manager, ***********************************************/ void build_essential_modules(ModuleManager& module_manager, const CircuitLibrary& circuit_lib) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building essential (inverter/buffer/logic gate) modules..."); for (const auto& circuit_model : circuit_lib.models()) { if (SPICE_MODEL_INVBUF == circuit_lib.model_type(circuit_model)) { @@ -163,6 +168,14 @@ void build_essential_modules(ModuleManager& module_manager, continue; } } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } /********************************************************************* @@ -173,6 +186,12 @@ void build_essential_modules(ModuleManager& module_manager, void build_user_defined_modules(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, const std::vector& routing_segments) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building user-defined modules..."); + /* Iterate over Verilog modules */ for (const auto& model : circuit_lib.models()) { /* We only care about user-defined models */ @@ -216,6 +235,14 @@ void build_user_defined_modules(ModuleManager& module_manager, BasicPort module_mid_output_port(generate_segment_wire_mid_output_name(circuit_lib.port_lib_name(output_ports[0])), circuit_lib.port_size(output_ports[0])); module_manager.add_port(module_id, module_mid_output_port, ModuleManager::MODULE_OUTPUT_PORT); } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } /********************************************************************* @@ -245,7 +272,7 @@ void build_constant_generator_modules(ModuleManager& module_manager) { clock_t t_start = clock(); vpr_printf(TIO_MESSAGE_INFO, - "Building modules for constant generator..."); + "Building constant generator modules..."); /* VDD */ build_constant_generator_module(module_manager, 1); @@ -258,6 +285,6 @@ void build_constant_generator_modules(ModuleManager& module_manager) { float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; vpr_printf(TIO_MESSAGE_INFO, - "took %g seconds\n", + "took %.2g seconds\n", run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp index 432cbde9b..f348cf870 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_grid_modules.cpp @@ -3,6 +3,7 @@ * (CLBs, I/Os, heterogeneous blocks etc.) *******************************************************************/ /* System header files */ +#include #include /* Header files from external libs */ @@ -1099,6 +1100,12 @@ void build_grid_modules(ModuleManager& module_manager, const MuxLibrary& mux_lib, const e_sram_orgz& sram_orgz_type, const CircuitModelId& sram_model) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building grid modules..."); + /* Enumerate the types, dump one Verilog module for each */ for (int itype = 0; itype < num_types; itype++) { if (EMPTY_TYPE == &type_descriptors[itype]) { @@ -1129,5 +1136,13 @@ void build_grid_modules(ModuleManager& module_manager, NUM_SIDES); } } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp index c7057712b..75795bd50 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_lut_modules.cpp @@ -2,6 +2,7 @@ * This file include functions that create modules for * the Look-Up Tables (LUTs) ********************************************************************/ +#include #include #include @@ -389,6 +390,11 @@ void build_lut_module(ModuleManager& module_manager, ********************************************************************/ void build_lut_modules(ModuleManager& module_manager, const CircuitLibrary& circuit_lib) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building Look-Up Table (LUT) modules..."); /* Search for each LUT circuit model */ for (const auto& lut_model : circuit_lib.models()) { @@ -398,5 +404,13 @@ void build_lut_modules(ModuleManager& module_manager, } build_lut_module(module_manager, circuit_lib, lut_model); } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp index d040fdc53..863c1bcc1 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_memory_modules.cpp @@ -3,6 +3,7 @@ * the memories that are affiliated to multiplexers and other programmable * circuit models, such as IOPADs, LUTs, etc. ********************************************************************/ +#include #include #include @@ -630,6 +631,11 @@ void build_memory_modules(ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib, const e_sram_orgz& sram_orgz_type) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building memory modules..."); /* Create the memory circuits for the multiplexer */ for (auto mux : mux_lib.muxes()) { @@ -677,5 +683,13 @@ void build_memory_modules(ModuleManager& module_manager, /* Create a Verilog module for the memories used by the circuit model */ build_memory_module(module_manager, circuit_lib, sram_orgz_type, module_name, sram_models[0], num_mems); } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp index 901947d80..2386000c5 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_mux_modules.cpp @@ -5,6 +5,7 @@ * such as a branch in a multiplexer * and the full multiplexer **********************************************/ +#include #include #include @@ -1369,6 +1370,11 @@ void build_mux_module(ModuleManager& module_manager, void build_mux_modules(ModuleManager& module_manager, const MuxLibrary& mux_lib, const CircuitLibrary& circuit_lib) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building multiplexer modules..."); /* Generate basis sub-circuit for unique branches shared by the multiplexers */ for (auto mux : mux_lib.muxes()) { @@ -1391,5 +1397,13 @@ void build_mux_modules(ModuleManager& module_manager, /* Create MUX circuits */ build_mux_module(module_manager, circuit_lib, mux_circuit_model, mux_graph); } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp index 019872fc3..b1c687e77 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_routing_modules.cpp @@ -5,6 +5,7 @@ * 1. Connection blocks * 2. Switch blocks *******************************************************************/ +#include #include #include "vtr_assert.h" @@ -1069,6 +1070,12 @@ void build_flatten_routing_modules(ModuleManager& module_manager, const std::vector>& grids, const t_det_routing_arch& routing_arch, const std::vector& rr_switches) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building routing modules..."); + /* We only support uni-directional routing architecture now */ VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality); @@ -1098,6 +1105,13 @@ void build_flatten_routing_modules(ModuleManager& module_manager, sram_orgz_type, sram_model, CHANY); + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } /******************************************************************** @@ -1119,6 +1133,12 @@ void build_unique_routing_modules(ModuleManager& module_manager, const std::vector>& grids, const t_det_routing_arch& routing_arch, const std::vector& rr_switches) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building unique routing modules..."); + /* We only support uni-directional routing architecture now */ VTR_ASSERT (UNI_DIRECTIONAL == routing_arch.directionality); @@ -1152,4 +1172,12 @@ void build_unique_routing_modules(ModuleManager& module_manager, sram_orgz_type, sram_model, unique_mirror, CHANY); } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp index f2e6539ac..9acb7bc59 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_top_module.cpp @@ -2,6 +2,7 @@ * This file includes functions that are used to print the top-level * module for the FPGA fabric in Verilog format *******************************************************************/ +#include #include #include @@ -831,6 +832,12 @@ void build_top_module(ModuleManager& module_manager, const e_sram_orgz& sram_orgz_type, const CircuitModelId& sram_model, const bool& compact_routing_hierarchy) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building FPGA fabric module..."); + /* Create a module as the top-level fabric, and add it to the module manager */ std::string top_module_name = generate_fpga_top_module_name(); ModuleId top_module = module_manager.add_module(top_module_name); @@ -900,4 +907,12 @@ void build_top_module(ModuleManager& module_manager, add_top_module_nets_memory_config_bus(module_manager, top_module, sram_orgz_type, circuit_lib.design_tech_type(sram_model)); } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); } diff --git a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp index 020329e63..f338110c8 100644 --- a/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp +++ b/vpr7_x2p/vpr/SRC/fpga_x2p/module_builder/build_wire_modules.cpp @@ -2,6 +2,7 @@ * This file includes functions to generate * Verilog submodules for wires. **********************************************/ +#include #include #include @@ -105,6 +106,12 @@ void build_routing_wire_module(ModuleManager& module_manager, void build_wire_modules(ModuleManager& module_manager, const CircuitLibrary& circuit_lib, std::vector routing_segments) { + /* Start time count */ + clock_t t_start = clock(); + + vpr_printf(TIO_MESSAGE_INFO, + "Building wire modules..."); + /* Print Verilog models for regular wires*/ for (const auto& wire_model : circuit_lib.models_by_type(SPICE_MODEL_WIRE)) { /* Bypass user-defined circuit models */ @@ -131,4 +138,12 @@ void build_wire_modules(ModuleManager& module_manager, /* Print a Verilog module */ build_routing_wire_module(module_manager, circuit_lib, seg.circuit_model, segment_wire_subckt_name); } + + /* End time count */ + clock_t t_end = clock(); + + float run_time_sec = (float)(t_end - t_start) / CLOCKS_PER_SEC; + vpr_printf(TIO_MESSAGE_INFO, + "took %.2g seconds\n", + run_time_sec); }