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[core] replace width syntax with global port name

This commit is contained in:
tangxifan 2024-06-29 10:46:00 -07:00
parent 67554cb8d8
commit 34fb003911
7 changed files with 30 additions and 16 deletions
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2
libs/libclkarchopenfpga/arch/example.xml
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@ -1,5 +1,5 @@
<clock_networks default_segment="seg_len1" default_tap_switch="fast_switch" default_driver_switch="slow_switch">
<clock_network name="example_network" width="8">
<clock_network name="example_network" global_port="clk[0:7]">
<spine name="spine_lvl3" start_x="0" start_y="2" end_x="2" end_y="2">
<switch_point tap="spine_lvl2_upper" x="2" y="2"/>
<switch_point tap="spine_lvl2_lower" x="2" y="2"/>

2
libs/libclkarchopenfpga/arch/example_internal_drivers.xml
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@ -1,5 +1,5 @@
<clock_networks default_segment="seg_len1" default_tap_switch="fast_switch" default_driver_switch="slow_switch">
<clock_network name="example_network" width="8">
<clock_network name="example_network" global_port="clk[0:7]">
<spine name="spine_lvl3" start_x="0" start_y="2" end_x="2" end_y="2">
<switch_point tap="spine_lvl2_upper" x="2" y="2">
<internal_driver tile_pin="clb.O[0:3]"/>

19
libs/libclkarchopenfpga/src/base/clock_network.cpp
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@ -217,9 +217,14 @@ size_t ClockNetwork::max_tree_depth() const {
return max_size;
}
BasicPort ClockNetwork::tree_global_port(const ClockTreeId& tree_id) const {
VTR_ASSERT(valid_tree_id(tree_id));
return tree_global_ports_[tree_id];
}
size_t ClockNetwork::tree_width(const ClockTreeId& tree_id) const {
VTR_ASSERT(valid_tree_id(tree_id));
return tree_widths_[tree_id];
return tree_global_ports_[tree_id].get_width();
}
size_t ClockNetwork::tree_depth(const ClockTreeId& tree_id) const {
@ -606,7 +611,7 @@ void ClockNetwork::reserve_spines(const size_t& num_spines) {
void ClockNetwork::reserve_trees(const size_t& num_trees) {
tree_ids_.reserve(num_trees);
tree_names_.reserve(num_trees);
tree_widths_.reserve(num_trees);
tree_global_ports_.reserve(num_trees);
tree_top_spines_.reserve(num_trees);
tree_taps_.reserve(num_trees);
}
@ -635,13 +640,19 @@ void ClockNetwork::set_default_driver_switch_name(const std::string& name) {
default_driver_switch_name_ = name;
}
ClockTreeId ClockNetwork::create_tree(const std::string& name, size_t width) {
ClockTreeId ClockNetwork::create_tree(const std::string& name, const BasicPort& global_port) {
/* Sanity checks */
if (!global_port.is_valid()) {
VTR_LOG_ERROR("Invalid global port '%s' for clock tree name '%s'\n",
global_port.to_verilog_string().c_str(), name.c_str());
exit(1);
}
/* Create a new id */
ClockTreeId tree_id = ClockTreeId(tree_ids_.size());
tree_ids_.push_back(tree_id);
tree_names_.push_back(name);
tree_widths_.push_back(width);
tree_global_ports_.push_back(global_port);
tree_depths_.emplace_back();
tree_taps_.emplace_back();
tree_top_spines_.emplace_back();

6
libs/libclkarchopenfpga/src/base/clock_network.h
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@ -16,6 +16,7 @@
#include "clock_network_fwd.h"
#include "rr_graph_fwd.h"
#include "rr_node_types.h"
#include "openfpga_port.h"
namespace openfpga { // Begin namespace openfpga
@ -87,6 +88,7 @@ class ClockNetwork {
RRSwitchId default_driver_switch() const;
std::string default_driver_switch_name() const;
std::string tree_name(const ClockTreeId& tree_id) const;
BasicPort tree_global_port(const ClockTreeId& tree_id) const;
size_t tree_width(const ClockTreeId& tree_id) const;
size_t tree_depth(const ClockTreeId& tree_id) const;
size_t max_tree_width() const;
@ -196,7 +198,7 @@ class ClockNetwork {
void set_default_driver_switch_name(const std::string& name);
/* Create a new tree, by default the tree can accomodate only 1 clock signal;
* use width to adjust the size */
ClockTreeId create_tree(const std::string& name, size_t width = 1);
ClockTreeId create_tree(const std::string& name, const BasicPort& global_port);
/* Create a new spine, if the spine is already created, return an invalid id
*/
ClockSpineId create_spine(const std::string& name);
@ -289,7 +291,7 @@ class ClockNetwork {
/* Basic information of each tree */
vtr::vector<ClockTreeId, ClockTreeId> tree_ids_;
vtr::vector<ClockTreeId, std::string> tree_names_;
vtr::vector<ClockTreeId, size_t> tree_widths_;
vtr::vector<ClockTreeId, BasicPort> tree_global_ports_;
vtr::vector<ClockTreeId, size_t> tree_depths_;
vtr::vector<ClockTreeId, std::vector<ClockSpineId>> tree_top_spines_;
vtr::vector<ClockTreeId, std::vector<ClockTapId>> tree_taps_;

2
libs/libclkarchopenfpga/src/io/clock_network_xml_constants.h
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@ -12,7 +12,7 @@ constexpr const char* XML_CLOCK_NETWORK_ATTRIBUTE_DEFAULT_DRIVER_SWITCH =
"default_driver_switch";
constexpr const char* XML_CLOCK_TREE_NODE_NAME = "clock_network";
constexpr const char* XML_CLOCK_TREE_ATTRIBUTE_NAME = "name";
constexpr const char* XML_CLOCK_TREE_ATTRIBUTE_WIDTH = "width";
constexpr const char* XML_CLOCK_TREE_ATTRIBUTE_GLOBAL_PORT = "global_port";
constexpr const char* XML_CLOCK_SPINE_NODE_NAME = "spine";
constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_NAME = "name";
constexpr const char* XML_CLOCK_SPINE_ATTRIBUTE_START_X = "start_x";

11
libs/libclkarchopenfpga/src/io/read_xml_clock_network.cpp
View File

@ -338,14 +338,15 @@ static void read_xml_clock_tree(pugi::xml_node& xml_clk_tree,
const pugiutil::loc_data& loc_data,
ClockNetwork& clk_ntwk) {
std::string clk_tree_name =
get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_NAME, loc_data)
get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_NAME, loc_data, pugiutil::ReqOpt::REQUIRED)
.as_string();
std::string clk_global_port_str =
get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_GLOBAL_PORT, loc_data, pugiutil::ReqOpt::REQUIRED)
.as_string();
int clk_tree_width =
get_attribute(xml_clk_tree, XML_CLOCK_TREE_ATTRIBUTE_WIDTH, loc_data)
.as_int();
/* Create a new tree in the storage */
ClockTreeId tree_id = clk_ntwk.create_tree(clk_tree_name, clk_tree_width);
PortParser gport_parser(clk_global_port_str);
ClockTreeId tree_id = clk_ntwk.create_tree(clk_tree_name, gport_parser.port());
if (false == clk_ntwk.valid_tree_id(tree_id)) {
archfpga_throw(loc_data.filename_c_str(), loc_data.line(xml_clk_tree),

4
libs/libclkarchopenfpga/src/io/write_xml_clock_network.cpp
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@ -194,8 +194,8 @@ static int write_xml_clock_tree(std::fstream& fp, const ClockNetwork& clk_ntwk,
write_xml_attribute(fp, XML_CLOCK_TREE_ATTRIBUTE_NAME,
clk_ntwk.tree_name(tree_id).c_str());
write_xml_attribute(fp, XML_CLOCK_TREE_ATTRIBUTE_WIDTH,
clk_ntwk.tree_width(tree_id));
write_xml_attribute(fp, XML_CLOCK_TREE_ATTRIBUTE_GLOBAL_PORT,
clk_ntwk.tree_global_port(tree_id).to_verilog_string().c_str());
fp << ">"
<< "\n";