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[Engine] Fixed a critical bug when building final bitstream, which may cause loss when merging BLs

This commit is contained in:
tangxifan 2021-09-25 20:22:27 -07:00
parent 29c351f5a4
commit 33e9b27cb8
3 changed files with 10 additions and 10 deletions
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8
openfpga/src/fpga_bitstream/write_text_fabric_bitstream.cpp
View File

@ -200,11 +200,11 @@ int write_memory_bank_flatten_fabric_bitstream_to_text_file(std::fstream& fp,
* just get it from the 1st element to save runtime
*/
size_t bl_addr_size = 0;
for (const auto& bl_vec : fabric_bits.begin()->first) {
for (const auto& bl_vec : fabric_bits.begin()->second) {
bl_addr_size += bl_vec.size();
}
size_t wl_addr_size = 0;
for (const auto& wl_vec : fabric_bits.begin()->second) {
for (const auto& wl_vec : fabric_bits.begin()->first) {
wl_addr_size += wl_vec.size();
}
@ -217,11 +217,11 @@ int write_memory_bank_flatten_fabric_bitstream_to_text_file(std::fstream& fp,
for (const auto& addr_pair : fabric_bits) {
/* Write BL address code */
for (const auto& bl_vec : addr_pair.first) {
for (const auto& bl_vec : addr_pair.second) {
fp << bl_vec;
}
/* Write WL address code */
for (const auto& wl_vec : addr_pair.second) {
for (const auto& wl_vec : addr_pair.first) {
fp << wl_vec;
}
fp << std::endl;

7
openfpga/src/utils/fabric_bitstream_utils.cpp
View File

@ -258,9 +258,6 @@ MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(cons
/* Place the config bit */
auto result = fabric_bits_per_region[region].find(wl_addr_str);
if (result == fabric_bits_per_region[region].end()) {
/* This is a new bit, resize the vector to the number of regions
* and deposit '0' to all the bits
*/
fabric_bits_per_region[region][wl_addr_str] = bl_addr_str;
} else {
VTR_ASSERT_SAFE(result != fabric_bits_per_region[region].end());
@ -297,7 +294,7 @@ MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(cons
max_blwl_sizes_per_region[region].second = std::max(max_blwl_sizes_per_region[region].second, fabric_bits_per_region[region].begin()->first.size());
}
/* Combine the bitstream from different region into a unique one. Now we follow the convention: use (BL, WL) pairs */
/* Combine the bitstream from different region into a unique one. Now we follow the convention: use (WL, BL) pairs */
MemoryBankFlattenFabricBitstream fabric_bits;
for (size_t ikey = 0; ikey < max_key_size; ikey++) {
/* Prepare the final BL/WL vectors to be added to the bitstream database */
@ -316,7 +313,7 @@ MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(cons
}
}
/* Add the pair to std map */
fabric_bits[cur_bl_vectors] = cur_wl_vectors;
fabric_bits[cur_wl_vectors] = cur_bl_vectors;
}
return fabric_bits;

5
openfpga/src/utils/fabric_bitstream_utils.h
View File

@ -37,6 +37,10 @@ FrameFabricBitstream build_frame_based_fabric_bitstream_by_address(const FabricB
size_t find_frame_based_fast_configuration_fabric_bitstream_size(const FabricBitstream& fabric_bitstream,
const bool& bit_value_to_skip);
/* Must use (WL, BL) as pairs in the map!!!
* This is because BL data may not be unique while WL must be unique
*/
typedef std::map<std::vector<std::string>, std::vector<std::string>> MemoryBankFlattenFabricBitstream;
/********************************************************************
* @ brief Reorganize the fabric bitstream for memory banks which use flatten or shift register to manipulate BL and WLs
* For each configuration region, we will merge BL address (which are 1-hot codes) under the same WL address
@ -57,7 +61,6 @@ size_t find_frame_based_fast_configuration_fabric_bitstream_size(const FabricBit
*
* @note the std::map may cause large memory footprint for large bitstream databases!
*******************************************************************/
typedef std::map<std::vector<std::string>, std::vector<std::string>> MemoryBankFlattenFabricBitstream;
MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(const FabricBitstream& fabric_bitstream,
const bool& bit_value_to_skip);