From 335347a74f8b1aebff9a6c665b4ddbe561332a62 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sat, 30 Oct 2021 15:48:25 -0700
Subject: [PATCH] [Test] Bug fix

---
 .../generate_bitstream_fix_device_example_script.openfpga       | 2 +-
 .../generate_bitstream/device_48x48/config/task.conf            | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga b/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga
index e5c963ecf..6ad6573f5 100644
--- a/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga
+++ b/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga
@@ -1,6 +1,6 @@
 # Run VPR for the 'and' design
 #--write_rr_graph example_rr_graph.xml
-vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling route --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
+vpr ${VPR_ARCH_FILE} ${VPR_TESTBENCH_BLIF} --clock_modeling ideal --route_chan_width ${OPENFPGA_VPR_ROUTE_CHAN_WIDTH} --device ${OPENFPGA_VPR_DEVICE_LAYOUT}
 
 # Read OpenFPGA architecture definition
 read_openfpga_arch -f ${OPENFPGA_ARCH_FILE}
diff --git a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf
index 959959d3b..211f9a861 100644
--- a/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf
+++ b/openfpga_flow/tasks/fpga_bitstream/generate_bitstream/device_48x48/config/task.conf
@@ -38,7 +38,7 @@ arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_ch
 bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/SAPone/rtl/*
 
 [SYNTHESIS_PARAM]
-bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_bram_dsp_dff_flow.ys
+bench_yosys_common=${PATH:OPENFPGA_PATH}/openfpga_flow/misc/ys_tmpl_yosys_vpr_dff_flow.ys
 bench0_top = SAPone
 
 [SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]