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Added vpr_fpga_verilog_print_simulation_ini option

This commit is contained in:
Ganesh Gore 2019-11-15 14:26:57 -07:00
parent c80cbfe8c9
commit 333d10c94c
1 changed files with 4 additions and 6 deletions
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10
openfpga_flow/scripts/run_fpga_flow.py
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@ -191,9 +191,8 @@ VeriPar.add_argument('--vpr_fpga_verilog_print_top_tb', action="store_true",
VeriPar.add_argument('--vpr_fpga_verilog_print_input_blif_tb', VeriPar.add_argument('--vpr_fpga_verilog_print_input_blif_tb',
action="store_true", help="Print testbench" + action="store_true", help="Print testbench" +
"for input blif file in Verilog Generator") "for input blif file in Verilog Generator")
VeriPar.add_argument('--vpr_fpga_verilog_print_modelsim_autodeck', type=str, VeriPar.add_argument('--vpr_fpga_verilog_print_simulation_ini', action="store_true",
help="Print modelsim " + help="Create simulation INI file")
"simulation script", metavar="<modelsim.ini_path>")
VeriPar.add_argument('--vpr_fpga_verilog_explicit_mapping', action="store_true", VeriPar.add_argument('--vpr_fpga_verilog_explicit_mapping', action="store_true",
help="Explicit Mapping") help="Explicit Mapping")
@ -721,9 +720,8 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False):
command += ["--fpga_verilog_include_signal_init"] command += ["--fpga_verilog_include_signal_init"]
if args.vpr_fpga_verilog_formal_verification_top_netlist: if args.vpr_fpga_verilog_formal_verification_top_netlist:
command += ["--fpga_verilog_print_formal_verification_top_netlist"] command += ["--fpga_verilog_print_formal_verification_top_netlist"]
if args.vpr_fpga_verilog_print_modelsim_autodeck: if args.vpr_fpga_verilog_print_simulation_ini:
command += ["--fpga_verilog_print_modelsim_autodeck", command += ["--fpga_verilog_print_simulation_ini"]
args.vpr_fpga_verilog_print_modelsim_autodeck]
if args.vpr_fpga_verilog_include_icarus_simulator: if args.vpr_fpga_verilog_include_icarus_simulator:
command += ["--fpga_verilog_include_icarus_simulator"] command += ["--fpga_verilog_include_icarus_simulator"]
if args.vpr_fpga_verilog_print_report_timing_tcl: if args.vpr_fpga_verilog_print_report_timing_tcl: