From 3331540ed6a7874c7cccde8ae38ed5d08714bd40 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 3 Aug 2023 14:24:22 -0700 Subject: [PATCH] [core] using config child type in bitstream generation --- .../src/fabric/build_fpga_core_wrapper_module.cpp | 2 +- openfpga/src/fabric/build_memory_modules.cpp | 4 ++++ .../src/fpga_bitstream/build_device_bitstream.cpp | 14 +++++++------- .../src/fpga_bitstream/build_grid_bitstream.cpp | 8 ++++---- openfpga/src/utils/module_manager_utils.cpp | 6 +++--- openfpga/src/utils/module_manager_utils.h | 2 +- 6 files changed, 20 insertions(+), 16 deletions(-) diff --git a/openfpga/src/fabric/build_fpga_core_wrapper_module.cpp b/openfpga/src/fabric/build_fpga_core_wrapper_module.cpp index 0be788f48..d79260583 100644 --- a/openfpga/src/fabric/build_fpga_core_wrapper_module.cpp +++ b/openfpga/src/fabric/build_fpga_core_wrapper_module.cpp @@ -381,7 +381,7 @@ int add_fpga_core_to_device_module_graph(ModuleManager& module_manager, /* Now fpga_core should be the only configurable child under the top-level * module */ - module_manager.add_configurable_child(new_top_module, top_module, 0, false); + module_manager.add_configurable_child(new_top_module, top_module, 0, ModuleManager::e_config_child_type::UNIFIED); return status; } diff --git a/openfpga/src/fabric/build_memory_modules.cpp b/openfpga/src/fabric/build_memory_modules.cpp index 64828066a..f2d8d4bd3 100644 --- a/openfpga/src/fabric/build_memory_modules.cpp +++ b/openfpga/src/fabric/build_memory_modules.cpp @@ -1392,6 +1392,10 @@ int add_physical_memory_module(ModuleManager& module_manager, size_t module_num_config_bits = find_module_num_config_bits_from_child_modules( module_manager, curr_module, circuit_lib, sram_model, CONFIG_MEM_FEEDTHROUGH); + /* No need to build a memory when there are no configuration bits required */ + if (module_num_config_bits == 0) { + return CMD_EXEC_SUCCESS; + } std::string phy_mem_module_name = generate_physical_memory_module_name(module_manager.module_name(curr_module), module_num_config_bits); ModuleId phy_mem_module = module_manager.find_module(phy_mem_module_name); if (!module_manager.valid_module_id(phy_mem_module)) { diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp index 98c3ce4e1..9e3d721f4 100644 --- a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp @@ -35,15 +35,15 @@ static size_t rec_estimate_device_bitstream_num_blocks( * actually configurable memory elements * We skip them in couting */ - if (0 == module_manager.logical_configurable_children(top_module).size()) { + if (0 == module_manager.num_configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL)) { return 0; } size_t num_configurable_children = - module_manager.logical_configurable_children(top_module).size(); + module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL).size(); for (size_t ichild = 0; ichild < num_configurable_children; ++ichild) { ModuleId child_module = - module_manager.logical_configurable_children(top_module)[ichild]; + module_manager.configurable_children(top_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild]; num_blocks += rec_estimate_device_bitstream_num_blocks(module_manager, child_module); } @@ -68,7 +68,7 @@ static size_t rec_estimate_device_bitstream_num_bits( /* If a child module has no configurable children, this is a leaf node * We can count it in. Otherwise, we should go recursively. */ - if (0 == module_manager.logical_configurable_children(parent_module).size()) { + if (0 == module_manager.num_configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)) { return 1; } @@ -105,7 +105,7 @@ static size_t rec_estimate_device_bitstream_num_bits( VTR_ASSERT_SAFE(parent_module != top_module); size_t num_configurable_children = - module_manager.logical_configurable_children(parent_module).size(); + module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL).size(); /* Frame-based configuration protocol will have 1 decoder * if there are more than 1 configurable children @@ -117,7 +117,7 @@ static size_t rec_estimate_device_bitstream_num_bits( for (size_t ichild = 0; ichild < num_configurable_children; ++ichild) { ModuleId child_module = - module_manager.logical_configurable_children(parent_module)[ichild]; + module_manager.configurable_children(parent_module, ModuleManager::e_config_child_type::PHYSICAL)[ichild]; num_bits += rec_estimate_device_bitstream_num_bits( module_manager, top_module, child_module, config_protocol); } @@ -193,7 +193,7 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx, /* Reserve child blocks for the top level block */ bitstream_manager.reserve_child_blocks( top_block, count_module_manager_module_configurable_children( - openfpga_ctx.module_graph(), top_module)); + openfpga_ctx.module_graph(), top_module), ModuleManager::e_config_child_type::PHYSICAL); /* Create bitstream from grids */ VTR_LOGV(verbose, "Building grid bitstream...\n"); diff --git a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp index 3f642b5fc..1caee205b 100644 --- a/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_grid_bitstream.cpp @@ -636,7 +636,7 @@ static void rec_build_physical_block_bitstream( VTR_ASSERT(true == module_manager.valid_module_id(pb_module)); /* Skip module with no configurable children */ - if (0 == module_manager.logical_configurable_children(pb_module).size()) { + if (0 == module_manager.num_configurable_children(pb_module, ModuleManager::e_config_child_type::LOGICAL)) { return; } @@ -653,7 +653,7 @@ static void rec_build_physical_block_bitstream( bitstream_manager.reserve_child_blocks( parent_configurable_block, count_module_manager_module_configurable_children(module_manager, - pb_module)); + pb_module, ModuleManager::e_config_child_type::PHYSICAL)); /* Recursively finish all the child pb_types*/ if (false == is_primitive_pb_type(physical_pb_type)) { @@ -748,7 +748,7 @@ static void build_physical_block_bitstream( VTR_ASSERT(true == module_manager.valid_module_id(grid_module)); /* Skip module with no configurable children */ - if (0 == module_manager.configurable_children(grid_module).size()) { + if (0 == module_manager.num_configurable_children(grid_module, ModuleManager::e_config_child_type::LOGICAL)) { return; } @@ -770,7 +770,7 @@ static void build_physical_block_bitstream( /* Reserve child blocks for new created block */ bitstream_manager.reserve_child_blocks( grid_configurable_block, count_module_manager_module_configurable_children( - module_manager, grid_module)); + module_manager, grid_module, ModuleManager::e_config_child_type::PHYSICAL)); /* Iterate over the capacity of the grid * Now each physical tile may have a number of logical blocks diff --git a/openfpga/src/utils/module_manager_utils.cpp b/openfpga/src/utils/module_manager_utils.cpp index 63252791f..87baecf78 100644 --- a/openfpga/src/utils/module_manager_utils.cpp +++ b/openfpga/src/utils/module_manager_utils.cpp @@ -86,11 +86,11 @@ void reserve_module_manager_module_nets(ModuleManager& module_manager, *children as well ******************************************************************************/ size_t count_module_manager_module_configurable_children( - const ModuleManager& module_manager, const ModuleId& module) { + const ModuleManager& module_manager, const ModuleId& module, const ModuleManager::e_config_child_type& config_child_type) { size_t num_config_children = 0; - for (const ModuleId& child : module_manager.logical_configurable_children(module)) { - if (0 != module_manager.logical_configurable_children(child).size()) { + for (const ModuleId& child : module_manager.configurable_children(module, config_child_type)) { + if (0 != module_manager.configurable_children(child, config_child_type).size()) { num_config_children++; } } diff --git a/openfpga/src/utils/module_manager_utils.h b/openfpga/src/utils/module_manager_utils.h index c9d42235a..b1e02d79f 100644 --- a/openfpga/src/utils/module_manager_utils.h +++ b/openfpga/src/utils/module_manager_utils.h @@ -42,7 +42,7 @@ void reserve_module_manager_module_nets(ModuleManager& module_manager, const ModuleId& module); size_t count_module_manager_module_configurable_children( - const ModuleManager& module_manager, const ModuleId& module); + const ModuleManager& module_manager, const ModuleId& module, const ModuleManager::e_config_child_type& config_child_type); std::pair find_module_manager_instance_module_info( const ModuleManager& module_manager, const ModuleId& parent,