From 32df673d728d7935734f8b154ae1128295041909 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Sat, 16 Sep 2023 18:35:33 -0700 Subject: [PATCH] [core] code format --- .../fpga_bitstream/build_device_bitstream.cpp | 5 ++- .../build_routing_bitstream.cpp | 34 +++++++++++-------- .../fpga_bitstream/build_routing_bitstream.h | 7 ++-- 3 files changed, 26 insertions(+), 20 deletions(-) diff --git a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp index 10a85baf8..2a589aebc 100644 --- a/openfpga/src/fpga_bitstream/build_device_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_device_bitstream.cpp @@ -220,9 +220,8 @@ BitstreamManager build_device_bitstream(const VprContext& vpr_ctx, VTR_LOGV(verbose, "Building routing bitstream...\n"); build_routing_bitstream( bitstream_manager, top_block, openfpga_ctx.module_graph(), - openfpga_ctx.module_name_map(), - openfpga_ctx.fabric_tile(), openfpga_ctx.arch().circuit_lib, - openfpga_ctx.mux_lib(), vpr_ctx.atom(), + openfpga_ctx.module_name_map(), openfpga_ctx.fabric_tile(), + openfpga_ctx.arch().circuit_lib, openfpga_ctx.mux_lib(), vpr_ctx.atom(), openfpga_ctx.vpr_device_annotation(), openfpga_ctx.vpr_routing_annotation(), vpr_ctx.device().rr_graph, openfpga_ctx.device_rr_gsb(), openfpga_ctx.flow_manager().compress_routing(), verbose); diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp index c35eebce1..2daf50108 100644 --- a/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp +++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.cpp @@ -452,9 +452,10 @@ static void build_connection_block_bitstream( static void build_connection_block_bitstreams( BitstreamManager& bitstream_manager, const ConfigBlockId& top_configurable_block, - const ModuleManager& module_manager, const ModuleNameMap& module_name_map, const FabricTile& fabric_tile, - const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, - const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const FabricTile& fabric_tile, const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, const AtomContext& atom_ctx, + const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const bool& compact_routing_hierarchy, const t_rr_type& cb_type, const bool& verbose) { @@ -501,7 +502,8 @@ static void build_connection_block_bitstreams( cb_module_name = generate_connection_block_module_name(cb_type, unique_cb_coord); } - ModuleId cb_module = module_manager.find_module(module_name_map.name(cb_module_name)); + ModuleId cb_module = + module_manager.find_module(module_name_map.name(cb_module_name)); VTR_ASSERT(true == module_manager.valid_module_id(cb_module)); /* Bypass empty blocks which have none configurable children */ @@ -596,9 +598,10 @@ static void build_connection_block_bitstreams( void build_routing_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& top_configurable_block, - const ModuleManager& module_manager, const ModuleNameMap& module_name_map, const FabricTile& fabric_tile, - const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, - const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const FabricTile& fabric_tile, const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, const AtomContext& atom_ctx, + const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const bool& compact_routing_hierarchy, const bool& verbose) { @@ -636,7 +639,8 @@ void build_routing_bitstream( unique_sb_coord.set_y(unique_mirror.get_sb_y()); sb_module_name = generate_switch_block_module_name(unique_sb_coord); } - ModuleId sb_module = module_manager.find_module(module_name_map.name(sb_module_name)); + ModuleId sb_module = + module_manager.find_module(module_name_map.name(sb_module_name)); VTR_ASSERT(true == module_manager.valid_module_id(sb_module)); /* Bypass empty blocks which have none configurable children */ @@ -725,17 +729,19 @@ void build_routing_bitstream( VTR_LOG("Generating bitstream for X-direction Connection blocks ..."); build_connection_block_bitstreams( - bitstream_manager, top_configurable_block, module_manager, module_name_map, fabric_tile, - circuit_lib, mux_lib, atom_ctx, device_annotation, routing_annotation, - rr_graph, device_rr_gsb, compact_routing_hierarchy, CHANX, verbose); + bitstream_manager, top_configurable_block, module_manager, module_name_map, + fabric_tile, circuit_lib, mux_lib, atom_ctx, device_annotation, + routing_annotation, rr_graph, device_rr_gsb, compact_routing_hierarchy, + CHANX, verbose); VTR_LOG("Done\n"); VTR_LOG("Generating bitstream for Y-direction Connection blocks ..."); build_connection_block_bitstreams( - bitstream_manager, top_configurable_block, module_manager, module_name_map, fabric_tile, - circuit_lib, mux_lib, atom_ctx, device_annotation, routing_annotation, - rr_graph, device_rr_gsb, compact_routing_hierarchy, CHANY, verbose); + bitstream_manager, top_configurable_block, module_manager, module_name_map, + fabric_tile, circuit_lib, mux_lib, atom_ctx, device_annotation, + routing_annotation, rr_graph, device_rr_gsb, compact_routing_hierarchy, + CHANY, verbose); VTR_LOG("Done\n"); } diff --git a/openfpga/src/fpga_bitstream/build_routing_bitstream.h b/openfpga/src/fpga_bitstream/build_routing_bitstream.h index 97f2553c2..c3af671bd 100644 --- a/openfpga/src/fpga_bitstream/build_routing_bitstream.h +++ b/openfpga/src/fpga_bitstream/build_routing_bitstream.h @@ -30,9 +30,10 @@ namespace openfpga { void build_routing_bitstream( BitstreamManager& bitstream_manager, const ConfigBlockId& top_configurable_block, - const ModuleManager& module_manager, const ModuleNameMap& module_name_map, const FabricTile& fabric_tile, - const CircuitLibrary& circuit_lib, const MuxLibrary& mux_lib, - const AtomContext& atom_ctx, const VprDeviceAnnotation& device_annotation, + const ModuleManager& module_manager, const ModuleNameMap& module_name_map, + const FabricTile& fabric_tile, const CircuitLibrary& circuit_lib, + const MuxLibrary& mux_lib, const AtomContext& atom_ctx, + const VprDeviceAnnotation& device_annotation, const VprRoutingAnnotation& routing_annotation, const RRGraphView& rr_graph, const DeviceRRGSB& device_rr_gsb, const bool& compact_routing_hierarchy, const bool& verbose);