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OpenFPGA
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[engine] syntax

This commit is contained in:
tangxifan 2022-09-28 11:39:37 -07:00
parent 51f54bbf20
commit 3285af4107
3 changed files with 20 additions and 13 deletions
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18
openfpga/src/annotation/annotate_clustering.cpp
View File

@ -7,6 +7,8 @@
#include "vtr_log.h"
#include "vtr_geometry.h"
#include "command_exit_codes.h"
#include "annotate_clustering.h"
/* begin namespace openfpga */
@ -15,12 +17,12 @@ namespace openfpga {
/* @brief Record the net remapping and local routing trace changes in annotation
* This is to ensure that the clustering annotation data structure is always up-to-date
*/
void annotate_post_routing_cluster_sync_results(const DeviceContext& device_ctx,
const ClusteringContext& cluster_ctx,
VprClusteringAnnotation& cluster_annotation) {
bool annotate_post_routing_cluster_sync_results(const DeviceContext& device_ctx,
const ClusteringContext& clustering_ctx,
VprClusteringAnnotation& clustering_annotation) {
VTR_LOG("Building annotation for post-routing and clustering synchornization results...");
for (const ClusterBlockId& cluster_blk_id : cluster_ctx.clb_nlist.blocks()) {
for (const ClusterBlockId& cluster_blk_id : clustering_ctx.clb_nlist.blocks()) {
/* Skip invalid ids */
if (!cluster_blk_id) {
continue;
@ -29,16 +31,18 @@ void annotate_post_routing_cluster_sync_results(const DeviceContext& device_ctx,
for (int ipin = 0; ipin < logical_block->pb_type->num_pins; ++ipin) {
ClusterNetId pre_routing_net_id = clustering_ctx.clb_nlist.block_net(cluster_blk_id, ipin);
ClusterNetId post_routing_net_id = ClusterNetId::INVALID();
auto search_result = clustering_ctx.post_routing_clb_pin_nets[cluster_blk_id].find(ipin);
if (search_result != clustering_ctx.post_routing_clb_pin_nets[cluster_blk_id].end()) {
auto search_result = clustering_ctx.post_routing_clb_pin_nets.at(cluster_blk_id).find(ipin);
if (search_result != clustering_ctx.post_routing_clb_pin_nets.at(cluster_blk_id).end()) {
post_routing_net_id = search_result->second;
}
if (post_routing_net_id) {
vpr_clustering_annotation.rename_net(cluster_blk_id, ipin, post_routing_net_id);
clustering_annotation.rename_net(cluster_blk_id, ipin, post_routing_net_id);
}
}
}
VTR_LOG("Done\n");
return CMD_EXEC_SUCCESS;
}
} /* end namespace openfpga */

6
openfpga/src/annotation/annotate_clustering.h
View File

@ -14,9 +14,9 @@
/* begin namespace openfpga */
namespace openfpga {
void annotate_post_routing_cluster_sync_results(const DeviceContext& device_ctx,
const ClusteringContext& cluster_ctx,
VprClusteringAnnotation& cluster_annotation);
bool annotate_post_routing_cluster_sync_results(const DeviceContext& device_ctx,
const ClusteringContext& clustering_ctx,
VprClusteringAnnotation& clustering_annotation);
} /* end namespace openfpga */

7
openfpga/src/base/openfpga_link_arch.cpp
View File

@ -157,9 +157,12 @@ int link_arch(OpenfpgaContext& openfpga_ctx,
cmd_context.option_enable(cmd, opt_verbose));
/* Annotate clustering results */
annotate_post_routing_cluster_sync_results(g_vpr_ctx.device(),
if (CMD_EXEC_FATAL_ERROR == annotate_post_routing_cluster_sync_results(g_vpr_ctx.device(),
g_vpr_ctx.clustering(),
openfpga_ctx.mutable_vpr_clustering_annotation());
openfpga_ctx.mutable_vpr_clustering_annotation())) {
return CMD_EXEC_FATAL_ERROR;
}
/* Annotate placement results */
annotate_mapped_blocks(g_vpr_ctx.device(),