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[FPGA-SPICE] Bug fix for pass gate transistor sizing

This commit is contained in:
tangxifan 2020-09-19 15:24:40 -06:00
parent aa078f079c
commit 3262ceb276
1 changed files with 0 additions and 1 deletions
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openfpga/src/fpga_spice/spice_passgate.cpp
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@ -243,7 +243,6 @@ int print_spice_transmission_gate_subckt(std::fstream& fp,
*/
float regular_pmos_bin_width = tech_lib.transistor_model_max_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
float total_pmos_width = circuit_lib.pass_gate_logic_pmos_size(circuit_model)
* tech_lib.model_pn_ratio(tech_model)
* tech_lib.transistor_model_min_width(tech_model, TECH_LIB_TRANSISTOR_PMOS);
int num_pmos_bins = std::ceil(total_pmos_width / regular_pmos_bin_width);
float last_pmos_bin_width = std::fmod(total_pmos_width, regular_pmos_bin_width);