diff --git a/openfpga_flow/benchmarks/Test_Modes/test_modes.act b/openfpga_flow/benchmarks/Test_Modes/test_modes.act new file mode 100644 index 000000000..a58956a8e --- /dev/null +++ b/openfpga_flow/benchmarks/Test_Modes/test_modes.act @@ -0,0 +1,67 @@ +cint01 0.485400 0.188600 +n01 0.489000 0.213200 +cint02 0.502400 0.203200 +n02 0.509200 0.195200 +cint03 0.507200 0.192200 +n03 0.502400 0.201600 +cint04 0.463200 0.199400 +n04 0.522000 0.191000 +n05 0.486800 0.204800 +reg0 0.463000 0.195400 +reg1 0.487400 0.196600 +reg2 0.506200 0.195000 +reg3 0.492200 0.208200 +reg4 0.507200 0.204800 +reg5 0.500400 0.200600 +reg6 0.500800 0.203400 +reg7 0.509600 0.198800 +reg8 0.492200 0.188000 +reg9 0.504800 0.204400 +reg10 0.507600 0.203200 +reg11 0.494200 0.203600 +clk 0.534600 0.203800 +a_0 0.478200 0.203800 +a_1 0.514800 0.208600 +a_2 0.505800 0.204600 +a_3 0.500000 0.195200 +b_0 0.530800 0.192800 +b_1 0.495800 0.195400 +b_2 0.496600 0.201200 +b_3 0.492000 0.200200 +cin 0.502600 0.202200 +e 0.495200 0.201000 +f 0.504000 0.203400 +g 0.498200 0.202000 +reg_a_0 0.478200 0.203800 +reg_a_1 0.514800 0.208600 +reg_a_2 0.505800 0.204600 +reg_a_3 0.500000 0.195200 +reg_b_0 0.530800 0.192800 +reg_b_1 0.495800 0.195400 +reg_b_2 0.496600 0.201200 +reg_b_3 0.492000 0.200200 +reg_cin 0.502600 0.202200 +sum_0 0.489000 0.213200 +sum_1 0.509200 0.195200 +sum_2 0.502400 0.201600 +sum_3 0.522000 0.191000 +cout 0.486800 0.204800 +ref0 0.000000 0.000000 +n57 0.478200 0.097457 +n62 0.514800 0.107387 +n67 0.505800 0.103487 +n72 0.500000 0.097600 +n77 0.530800 0.102338 +n82 0.495800 0.096879 +n87 0.496600 0.099916 +n92 0.492000 0.098498 +n97 0.502600 0.101626 +d0 0.617800 0.046719 +x 0.492200 0.102476 +y 0.509600 0.101308 +z 0.494200 0.100619 +n102 0.489000 0.104255 +n106 0.509200 0.099396 +n110 0.502400 0.101284 +n114 0.522000 0.099702 +n118 0.486800 0.099697 diff --git a/openfpga_flow/benchmarks/Test_Modes/test_modes.blif b/openfpga_flow/benchmarks/Test_Modes/test_modes.blif new file mode 100644 index 000000000..f7ed4cb33 --- /dev/null +++ b/openfpga_flow/benchmarks/Test_Modes/test_modes.blif @@ -0,0 +1,94 @@ +# Benchmark "test" written by ABC on Tue Apr 30 17:17:10 2019 +.model test_modes +.inputs clk a_0 a_1 a_2 a_3 b_0 b_1 b_2 b_3 cin e f g +.outputs sum_0 sum_1 sum_2 sum_3 cout x y z + +.latch n57 reg_a_0 re clk 0 +.latch n62 reg_a_1 re clk 0 +.latch n67 reg_a_2 re clk 0 +.latch n72 reg_a_3 re clk 0 +.latch n77 reg_b_0 re clk 0 +.latch n82 reg_b_1 re clk 0 +.latch n87 reg_b_2 re clk 0 +.latch n92 reg_b_3 re clk 0 +.latch n97 reg_cin re clk 0 +.latch n102 sum_0 re clk 0 +.latch n106 sum_1 re clk 0 +.latch n110 sum_2 re clk 0 +.latch n114 sum_3 re clk 0 +.latch n118 cout re clk 0 + + +.subckt adder a=reg_a_0 b=reg_b_0 cin=reg_cin cout=cint01 sumout=n01 +.subckt adder a=reg_a_1 b=reg_b_1 cin=cint01 cout=cint02 sumout=n02 +.subckt adder a=reg_a_2 b=reg_b_2 cin=cint02 cout=cint03 sumout=n03 +.subckt adder a=reg_a_3 b=reg_b_3 cin=cint03 cout=cint04 sumout=n04 +.subckt adder a=ref0 b=ref0 cin=cint04 cout=unconn sumout=n05 + +.subckt shift D=d0 clk=clk Q=reg0 +.subckt shift D=reg0 clk=clk Q=reg1 +.subckt shift D=reg1 clk=clk Q=reg2 +.subckt shift D=reg2 clk=clk Q=reg3 +.subckt shift D=reg3 clk=clk Q=reg4 +.subckt shift D=reg4 clk=clk Q=reg5 +.subckt shift D=reg5 clk=clk Q=reg6 +.subckt shift D=reg6 clk=clk Q=reg7 +.subckt shift D=reg7 clk=clk Q=reg8 +.subckt shift D=reg8 clk=clk Q=reg9 +.subckt shift D=reg9 clk=clk Q=reg10 +.subckt shift D=reg10 clk=clk Q=reg11 + +.names ref0 + 0 +.names a_0 n57 +1 1 +.names a_1 n62 +1 1 +.names a_2 n67 +1 1 +.names a_3 n72 +1 1 +.names b_0 n77 +1 1 +.names b_1 n82 +1 1 +.names b_2 n87 +1 1 +.names b_3 n92 +1 1 +.names cin n97 +1 1 +.names e f g d0 +1-1 1 +-0- 1 +.names reg3 x +1 1 +.names reg7 y +1 1 +.names reg11 z +1 1 +.names n01 n102 +1 1 +.names n02 n106 +1 1 +.names n03 n110 +1 1 +.names n04 n114 +1 1 +.names n05 n118 +1 1 +.end + + +.model adder +.inputs a b cin +.outputs cout sumout +.blackbox +.end + + +.model shift +.inputs D clk +.outputs Q +.blackbox +.end diff --git a/openfpga_flow/benchmarks/Test_Modes/test_modes.v b/openfpga_flow/benchmarks/Test_Modes/test_modes.v new file mode 100644 index 000000000..8090d2903 --- /dev/null +++ b/openfpga_flow/benchmarks/Test_Modes/test_modes.v @@ -0,0 +1,78 @@ +//////////////////////////////////////////////////////// +// // +// Benchmark using all modes of k8 architecture // +// // +//////////////////////////////////////////////////////// + +`timescale 1 ns/ 1 ps + +module test_modes( + clk, + a_0, + a_1, + a_2, + a_3, + b_0, + b_1, + b_2, + b_3, + cin, + e, + f, + g, + sum_0, + sum_1, + sum_2, + sum_3, + cout, + x, + y, + z ); + + input wire clk, a_0, a_1, a_2, a_3, b_0, b_1, b_2, b_3, cin, e, f, g; + output reg sum_0, sum_1, sum_2, sum_3, cout; + output wire x, y, z; + + wire d0; + wire [4:0] n0; + wire [3:0] a, b; + reg reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8, reg9, reg10, reg11, reg_a_0, reg_a_1, reg_a_2, reg_a_3, reg_b_0, reg_b_1, reg_b_2, reg_b_3, reg_cin; + + assign a = {reg_a_3, reg_a_2, reg_a_1, reg_a_0}; + assign b = {reg_b_3, reg_b_2, reg_b_1, reg_b_0}; + assign d0 = (e && g) || !f; + assign n0 = a + b + reg_cin; + assign x = reg3; + assign y = reg7; + assign z = reg11; + + always @(posedge clk) begin + reg0 <= d0; + reg1 <= reg0; + reg2 <= reg1; + reg3 <= reg2; + reg4 <= reg3; + reg5 <= reg4; + reg6 <= reg5; + reg7 <= reg6; + reg8 <= reg7; + reg9 <= reg8; + reg10 <= reg9; + reg11 <= reg10; + reg_a_0 <= a_0; + reg_a_1 <= a_1; + reg_a_2 <= a_2; + reg_a_3 <= a_3; + reg_b_0 <= b_0; + reg_b_1 <= b_1; + reg_b_2 <= b_2; + reg_b_3 <= b_3; + reg_cin <= cin; + sum_0 <= n0[0]; + sum_1 <= n0[1]; + sum_2 <= n0[2]; + sum_3 <= n0[3]; + cout <= n0[4]; + end + +endmodule diff --git a/openfpga_flow/misc/fpgaflow_default_tool_path.conf b/openfpga_flow/misc/fpgaflow_default_tool_path.conf index d33fc4e80..d41183ac8 100644 --- a/openfpga_flow/misc/fpgaflow_default_tool_path.conf +++ b/openfpga_flow/misc/fpgaflow_default_tool_path.conf @@ -13,7 +13,7 @@ iverilog_path = iverilog include_netlist_verification = ${PATH:OPENFPGA_PATH}/vpr7_x2p/vpr/VerilogNetlists [FLOW_SCRIPT_CONFIG] -valid_flows = standard,vtr,vtr_standard,yosys_vpr +valid_flows = standard,vpr_blif,vtr,vtr_standard,yosys_vpr [DEFAULT_PARSE_RESULT_VPR] # parser format = , diff --git a/openfpga_flow/scripts/run_fpga_flow.py b/openfpga_flow/scripts/run_fpga_flow.py index b3d5adef7..1844abb95 100644 --- a/openfpga_flow/scripts/run_fpga_flow.py +++ b/openfpga_flow/scripts/run_fpga_flow.py @@ -60,6 +60,13 @@ parser.add_argument('--yosys_tmpl', type=str, parser.add_argument('--debug', action="store_true", help="Run script in debug mode") +# Blif_VPR Only flow arguments +parser.add_argument('--activity_file', type=str, + help="Activity file used while running yosys flow") +parser.add_argument('--base_verilog', type=str, + help="Original Verilog file to run verification in " + + "blif_VPR flow") + # ACE2 and power estimation related arguments parser.add_argument('--K', type=int, help="LUT Size, if not specified extracted from arch file") @@ -99,6 +106,8 @@ X2PParse.add_argument('--vpr_fpga_x2p_signal_density_weight', type=float, help="Specify the signal_density_weight of VPR FPGA SPICE") X2PParse.add_argument('--vpr_fpga_x2p_sim_window_size', type=float, help="specify the sim_window_size of VPR FPGA SPICE") +X2PParse.add_argument('--vpr_fpga_x2p_compact_routing_hierarchy', + action="store_true", help="Compact_routing_hierarchy") # VPR - FPGA-SPICE Extension SPParse = parser.add_argument_group('FPGA-SPICE Extension') @@ -162,6 +171,8 @@ VeriPar.add_argument('--vpr_fpga_verilog_print_input_blif_tb', VeriPar.add_argument('--vpr_fpga_verilog_print_modelsim_autodeck', type=str, help="Print modelsim " + "simulation script", metavar="") +VeriPar.add_argument('--vpr_fpga_verilog_explicit_mapping', action="store_true", + help="Explicit Mapping") # VPR - FPGA-Bitstream Extension BSparse = parser.add_argument_group('FPGA-Bitstream Extension') @@ -199,15 +210,17 @@ def main(): if (args.fpga_flow == "yosys_vpr"): logger.info('Running "yosys_vpr" Flow') run_yosys_with_abc() - if (args.fpga_flow == "vtr"): - run_odin2() - run_abc_vtr() - if (args.fpga_flow == "vtr_standard"): - run_abc_for_standarad() + run_rewrite_verilog() if args.power: run_ace2() run_pro_blif_3arg() - run_rewrite_verilog() + if (args.fpga_flow == "vpr_blif"): + collect_files_for_vpr() + # if (args.fpga_flow == "vtr"): + # run_odin2() + # run_abc_vtr() + # if (args.fpga_flow == "vtr_standard"): + # run_abc_for_standarad() run_vpr() if args.end_flow_with_test: run_netlists_verification() @@ -295,6 +308,10 @@ def validate_command_line_arguments(): # Expand run directory to absolute path args.run_dir = os.path.abspath(args.run_dir) + if args.activity_file: + args.activity_file = os.path.abspath(args.activity_file) + if args.base_verilog: + args.base_verilog = os.path.abspath(args.base_verilog) def ask_user_quetion(condition, question): @@ -499,6 +516,7 @@ def run_pro_blif_3arg(): def run_vpr(): + if not args.fix_route_chan_width: # Run Standard VPR Flow min_channel_width = run_standard_vpr( args.top_module+".blif", @@ -573,7 +591,7 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): command += ["--timing_driven_clustering", "off"] # channel width option if fixed_chan_width >= 0: - command += ["--route_chan_width", "%d"%fixed_chan_width] + command += ["--route_chan_width", "%d" % fixed_chan_width] if args.vpr_use_tileable_route_chan_width: command += ["--use_tileable_route_chan_width"] @@ -586,6 +604,9 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): if args.vpr_fpga_x2p_sim_window_size: command += ["--fpga_x2p_sim_window_size", args.vpr_fpga_x2p_sim_window_size] + if args.vpr_fpga_x2p_compact_routing_hierarchy: + command += ["--fpga_x2p_compact_routing_hierarchy"] + if args.vpr_fpga_spice_sim_mt_num: command += ["--fpga_spice_sim_mt_num", args.vpr_fpga_spice_sim_mt_num] @@ -627,6 +648,8 @@ def run_standard_vpr(bench_blif, fixed_chan_width, logfile, route_only=False): args.top_module+"_output_verilog.v"] if args.vpr_fpga_verilog_include_timing: command += ["--fpga_verilog_include_timing"] + if args.vpr_fpga_verilog_explicit_mapping: + command += ["--fpga_verilog_explicit_mapping"] if args.vpr_fpga_verilog_include_signal_init: command += ["--fpga_verilog_include_signal_init"] if args.vpr_fpga_verilog_formal_verification_top_netlist: