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[Doc] Update doc to deprecate anything related to '--support_icarus_simulator' and '--include_signal_init'

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tangxifan 2021-06-25 15:27:15 -06:00
parent 991062e9bf
commit 30027b8c15
2 changed files with 15 additions and 16 deletions
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16
docs/source/manual/fpga_verilog/testbench.rst
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@ -88,22 +88,6 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n
.. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled! .. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled!
- ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_verilog_testbench`` command.
.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
.. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
- ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_verilog_testbench`` command.
.. warning:: Please disable this flag if you are not using icarus iVerilog simulator.
__ iverilog_website_
.. _iverilog_website: http://iverilog.icarus.com/
.. option:: <bench_name>_autocheck_top_tb.v .. option:: <bench_name>_autocheck_top_tb.v
This is the netlist for full testbench. This is the netlist for full testbench.

15
docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
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@ -76,6 +76,11 @@ write_full_testbench
Output signal initialization to Verilog testbench to smooth convergence in HDL simulation Output signal initialization to Verilog testbench to smooth convergence in HDL simulation
.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
.. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
.. option:: --verbose .. option:: --verbose
Show verbose log Show verbose log
@ -112,10 +117,20 @@ write_preconfigured_fabric_wrapper
.. warning:: If the option ``none`` is selected, bitstream will not be embedded. Users should force the bitstream through HDL simulator commands. Otherwise, functionality of the wrapper netlist is wrong! .. warning:: If the option ``none`` is selected, bitstream will not be embedded. Users should force the bitstream through HDL simulator commands. Otherwise, functionality of the wrapper netlist is wrong!
.. warning:: Please specify ``iverilog`` if you are using icarus iVerilog simulator.
__ iverilog_website_
.. _iverilog_website: http://iverilog.icarus.com/
.. option:: --include_signal_init .. option:: --include_signal_init
Output signal initialization to Verilog testbench to smooth convergence in HDL simulation Output signal initialization to Verilog testbench to smooth convergence in HDL simulation
.. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
.. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
.. option:: --verbose .. option:: --verbose
Show verbose log Show verbose log