diff --git a/docs/source/manual/fpga_verilog/testbench.rst b/docs/source/manual/fpga_verilog/testbench.rst
index 3f41f1a1d..addf4496f 100644
--- a/docs/source/manual/fpga_verilog/testbench.rst
+++ b/docs/source/manual/fpga_verilog/testbench.rst
@@ -87,23 +87,7 @@ Inside the directory, the Verilog testbenches are organized as illustrated in :n
    - ```define ENABLE_FORMAL_SIMULATION`` When enabled, the ``<bench_name>_include_netlist.v`` will include the testbench netlist for formal-oriented simulation. This flag is added when ``--print_preconfig_top_testbench`` option is enabled when calling the ``write_verilog_testbench`` command. 
 
    .. note:: To run full testbenches, both flags ``ENABLE_FORMAL_VERIFICATION`` and ``ENABLE_FORMAL_SIMULATION`` must be disabled!
-
-   - ```define ENABLE_SIGNAL_INITIALIZATION`` When enabled, all the outputs of primitive Verilog modules will be initialized with a random value. This flag is added when ``--include_signal_init`` option is enabled when calling the ``write_verilog_testbench`` command. 
-
-   .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
-
-   .. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
    
-   - ```define ICARUS_SIMULATOR`` When enabled, Verilog netlists are generated to be compatible with the syntax required by `icarus iVerilog simulator`__. This flag is added when ``--support_icarus_simulator`` option is enabled when calling the ``write_verilog_testbench`` command. 
-
-   .. warning:: Please disable this flag if you are not using icarus iVerilog simulator.
-
-__ iverilog_website_
-
-.. _iverilog_website: http://iverilog.icarus.com/
-
-
-
 .. option:: <bench_name>_autocheck_top_tb.v
 
   This is the netlist for full testbench.
diff --git a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
index 957eb6e63..d8e254a3e 100644
--- a/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
+++ b/docs/source/manual/openfpga_shell/openfpga_commands/fpga_verilog_commands.rst
@@ -76,6 +76,11 @@ write_full_testbench
 
     Output signal initialization to Verilog testbench to smooth convergence in HDL simulation
 
+    .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
+
+   .. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
+
+
   .. option:: --verbose
 
     Show verbose log
@@ -112,10 +117,20 @@ write_preconfigured_fabric_wrapper
 
     .. warning:: If the option ``none`` is selected, bitstream will not be embedded. Users should force the bitstream through HDL simulator commands. Otherwise, functionality of the wrapper netlist is wrong!
 
+   .. warning:: Please specify ``iverilog`` if you are using icarus iVerilog simulator.
+
+__ iverilog_website_
+
+.. _iverilog_website: http://iverilog.icarus.com/
+
   .. option:: --include_signal_init
 
     Output signal initialization to Verilog testbench to smooth convergence in HDL simulation
 
+    .. note:: We strongly recommend users to turn on this flag as it can help simulators to converge quickly.
+
+   .. warning:: Signal initialization is only applied to the datapath inputs of routing multiplexers (considering the fact that they are indispensible cells of FPGAs)! If your FPGA does not contain any multiplexer cells, signal initialization is not applicable.
+
   .. option:: --verbose
 
     Show verbose log