From 2ff3ad61cea2e4c13e30d427a60ae4b674f53abb Mon Sep 17 00:00:00 2001 From: tangxifan Date: Mon, 6 Mar 2023 21:57:44 -0800 Subject: [PATCH] [core] format --- openfpga/src/annotation/append_clock_rr_graph.cpp | 11 +++++++---- openfpga/src/base/openfpga_link_arch_template.h | 8 ++++---- openfpga/src/mux_lib/mux_library_builder.cpp | 6 +++++- 3 files changed, 16 insertions(+), 9 deletions(-) diff --git a/openfpga/src/annotation/append_clock_rr_graph.cpp b/openfpga/src/annotation/append_clock_rr_graph.cpp index 0f848ff36..81159d5bf 100644 --- a/openfpga/src/annotation/append_clock_rr_graph.cpp +++ b/openfpga/src/annotation/append_clock_rr_graph.cpp @@ -505,8 +505,9 @@ static void add_rr_graph_block_clock_edges( for (size_t ipin = 0; ipin < num_pins / 2; ++ipin) { for (auto node_dir : {Direction::INC, Direction::DEC}) { /* find the driver clock node through lookup */ - RRNodeId src_node = clk_rr_lookup.find_node( - chan_coord.x(), chan_coord.y(), itree, ilvl, ClockTreePinId(ipin), node_dir); + RRNodeId src_node = + clk_rr_lookup.find_node(chan_coord.x(), chan_coord.y(), itree, ilvl, + ClockTreePinId(ipin), node_dir); VTR_LOGV(verbose, "Try to find node '%lu' from clock node lookup (x='%lu' " "y='%lu' tree='%lu' level='%lu' pin='%lu' direction='%s')\n", @@ -526,7 +527,8 @@ static void add_rr_graph_block_clock_edges( clk_ntwk.default_switch()); edge_count++; } - VTR_LOGV(verbose, "\tWill add %lu edges to other clock nodes\n", edge_count - curr_edge_count); + VTR_LOGV(verbose, "\tWill add %lu edges to other clock nodes\n", + edge_count - curr_edge_count); } /* If this is the clock node at the last level of the tree, * should drive some grid IPINs which are clocks */ @@ -541,7 +543,8 @@ static void add_rr_graph_block_clock_edges( clk_ntwk.default_switch()); edge_count++; } - VTR_LOGV(verbose, "\tWill add %lu edges to other IPIN\n", edge_count - curr_edge_count); + VTR_LOGV(verbose, "\tWill add %lu edges to other IPIN\n", + edge_count - curr_edge_count); } } } diff --git a/openfpga/src/base/openfpga_link_arch_template.h b/openfpga/src/base/openfpga_link_arch_template.h index 2c6fa787c..d9345780c 100644 --- a/openfpga/src/base/openfpga_link_arch_template.h +++ b/openfpga/src/base/openfpga_link_arch_template.h @@ -108,10 +108,10 @@ int link_arch_template(T& openfpga_ctx, const Command& cmd, VTR_LOG("Built %ld incoming edges for routing resource graph\n", g_vpr_ctx.device().rr_graph.in_edges_count()); VTR_ASSERT(g_vpr_ctx.device().rr_graph.validate_in_edges()); - annotate_device_rr_gsb(g_vpr_ctx.device(), - openfpga_ctx.mutable_device_rr_gsb(), - !openfpga_ctx.clock_arch().empty(), /* FIXME: consider to be more robust! */ - cmd_context.option_enable(cmd, opt_verbose)); + annotate_device_rr_gsb( + g_vpr_ctx.device(), openfpga_ctx.mutable_device_rr_gsb(), + !openfpga_ctx.clock_arch().empty(), /* FIXME: consider to be more robust! */ + cmd_context.option_enable(cmd, opt_verbose)); if (true == cmd_context.option_enable(cmd, opt_sort_edge)) { sort_device_rr_gsb_chan_node_in_edges( diff --git a/openfpga/src/mux_lib/mux_library_builder.cpp b/openfpga/src/mux_lib/mux_library_builder.cpp index 9dbe78253..4cf4b62c3 100644 --- a/openfpga/src/mux_lib/mux_library_builder.cpp +++ b/openfpga/src/mux_lib/mux_library_builder.cpp @@ -232,7 +232,11 @@ MuxLibrary build_device_mux_library(const DeviceContext& vpr_device_ctx, mux_lib.muxes().size()); VTR_LOG("Maximum multiplexer size is %lu.\n", mux_lib.max_mux_size()); for (auto mux_id : mux_lib.muxes()) { - VTR_LOG("\tmodel '%s', input_size='%lu'\n", openfpga_ctx.arch().circuit_lib.model_name(mux_lib.mux_circuit_model(mux_id)).c_str(), mux_lib.mux_graph(mux_id).num_inputs()); + VTR_LOG("\tmodel '%s', input_size='%lu'\n", + openfpga_ctx.arch() + .circuit_lib.model_name(mux_lib.mux_circuit_model(mux_id)) + .c_str(), + mux_lib.mux_graph(mux_id).num_inputs()); } return mux_lib;