From 2fee56548baa499054b32d1259ca7acaadcacb5b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Wed, 6 Sep 2023 22:39:59 -0700 Subject: [PATCH] [core] fixed some bugs --- .../src/fpga_verilog/verilog_writer_utils.cpp | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp index a6dc76e8a..64e8e8aac 100644 --- a/openfpga/src/fpga_verilog/verilog_writer_utils.cpp +++ b/openfpga/src/fpga_verilog/verilog_writer_utils.cpp @@ -32,15 +32,9 @@ void print_verilog_default_net_type_declaration( std::fstream& fp, const e_verilog_default_net_type& default_net_type) { VTR_ASSERT(true == valid_file_stream(fp)); - if (default_net_type != VERILOG_DEFAULT_NET_TYPE_WIRE) { - fp << "//----- Default net type -----" << std::endl; - fp << "`default_nettype " - << VERILOG_DEFAULT_NET_TYPE_STRING[default_net_type] << std::endl; - } else { - fp << "//----- Assume default net type to be " - << VERILOG_DEFAULT_NET_TYPE_STRING[VERILOG_DEFAULT_NET_TYPE_WIRE] - << "-----" << std::endl; - } + fp << "//----- Default net type -----" << std::endl; + fp << "`default_nettype " + << VERILOG_DEFAULT_NET_TYPE_STRING[default_net_type] << std::endl; fp << std::endl; } @@ -347,7 +341,9 @@ void print_verilog_module_declaration( VTR_ASSERT(true == valid_file_stream(fp)); /* Apply default net type from user's option */ - print_verilog_default_net_type_declaration(fp, default_net_type); + if (default_net_type != VERILOG_DEFAULT_NET_TYPE_WIRE) { + print_verilog_default_net_type_declaration(fp, default_net_type); + } print_verilog_module_definition(fp, module_manager, module_id);