Adding DPRAM behavioural Verilog netlist and its TB

openfpga_flow/VerilogNetlists/dpram.v

@@ -1,20 +1,20 @@
 //-----------------------------------------------------
-// Design Name : dual_port_ram_32x512
-// File Name   : dpram.v
-// Function    : Dual port RAM 32x512
-// Coder       : Aurelien Alacchi
+// Design Name : dual_port_ram
+// File Name   : memory_wrapper.v
+// Function    : Dual port RAM 64x2048 
+// Coder       : Aurelien
 //-----------------------------------------------------
 
-module dual_port_ram_32x512 (
+module dpram (
 	input clk,
 	input wen,
 	input ren,
-	input[0:8] waddr,
-	input[0:8] raddr,
+	input[0:9] waddr,
+	input[0:9] raddr,
 	input[0:31] d_in,
 	output[0:31] d_out );
 
-		dual_port_sram_32x512 memory_0 (
+		dual_port_sram memory_0 (
 			.wclk		(clk),
 			.wen		(wen),
 			.waddr		(waddr),
@@ -26,28 +26,28 @@ module dual_port_ram_32x512 (
 
 endmodule
 
-module dual_port_sram_32x512 (
+module dual_port_sram (
 	input wclk,
 	input wen,
-	input[0:8] waddr,
+	input[0:9] waddr,
 	input[0:31] data_in,
 	input rclk,
 	input ren,
-	input[0:8] raddr,
+	input[0:9] raddr,
 	output[0:31] d_out );
 
-	reg[0:31] ram[0:511];
+	reg[0:31] ram[0:1023];
 	reg[0:31] internal;
 
 	assign d_out = internal;
 
-	always @(posedge wclk) begin
+	always @(negedge wclk) begin
 		if(wen) begin
 			ram[waddr] <= data_in;
 		end
 	end
 
-	always @(posedge rclk) begin
+	always @(negedge rclk) begin
 		if(ren) begin
 			internal <= ram[raddr];
 		end

openfpga_flow/VerilogNetlists/dpram_tb.v

@@ -0,0 +1,61 @@
+//-----------------------------------------------------
+// Design Name : dual_port_ram_tb
+// File Name   : memory_wrapper_tb.v
+// Function    : Dual port RAM 64x2048 
+// Coder       : Aurelien
+//-----------------------------------------------------
+`timescale 1 ns/1 ps
+
+module dpram_tb ();
+	reg clk;
+	reg wen;
+	reg ren;
+	reg[0:9] waddr;
+	reg[0:9] raddr;
+	reg[0:31] d_in;
+	wire[0:31] d_out;
+
+	integer count;
+	integer lim_max = 1023;
+
+		dpram memory_0 (
+			.clk		(clk),
+			.wen		(wen),
+			.waddr		(waddr),
+			.d_in		(d_in),
+			.ren		(ren),
+			.raddr		(raddr),
+			.d_out		(d_out) );
+
+	initial begin
+		clk <= 1'b0;
+		ren <= 1'b0;
+		wen <= 1'b0;
+		raddr <= 10'h000;
+		waddr <= 10'h000;
+		d_in <= 32'h00000000;
+		for(count = 0; count < lim_max; count = count +1) begin
+			#5
+			wen <= 1'b1;
+			clk <= !clk;
+			if(clk) begin
+				waddr <= waddr + 1;
+			end
+		end	
+		wen <= 1'b0;
+		for(count = 0; count < lim_max; count = count +1) begin
+			#5
+			ren <= 1'b1;
+			clk <= !clk;
+			if(clk) begin
+				raddr <= raddr + 1;
+			end
+		end	
+		$finish;
+	end
+
+	always@(negedge clk) begin
+		d_in <= $random;
+	end
+
+endmodule