From 2e88b035ed12a9eae99efb28c64d8b068f491bd8 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 18 Feb 2021 17:55:26 -0700 Subject: [PATCH] [Test] Add wire LUT repacker test case --- .../repack_wire_lut/config/task.conf | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 openfpga_flow/tasks/fpga_bitstream/repack_wire_lut/config/task.conf diff --git a/openfpga_flow/tasks/fpga_bitstream/repack_wire_lut/config/task.conf b/openfpga_flow/tasks/fpga_bitstream/repack_wire_lut/config/task.conf new file mode 100644 index 000000000..856f935c4 --- /dev/null +++ b/openfpga_flow/tasks/fpga_bitstream/repack_wire_lut/config/task.conf @@ -0,0 +1,37 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +# Runtime of this bitstream generation should not exceed 6 minutes as a QoR requirement +timeout_each_job = 1*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/generate_bitstream_fix_device_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10_adder_register_scan_chain_depop50_40nm_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_route_chan_width=200 +openfpga_vpr_device_layout=auto + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmarks/FIR_filter/FIR_filter_firBlock_left_debug.blif + +[SYNTHESIS_PARAM] +bench0_top=FIR_filter_firBlock_left +bench0_act=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmarks/FIR_filter/FIR_filter_firBlock_left_ace_out_debug.act +bench0_verilog=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmarks/FIR_filter/FIR_filter_firBlock_left_output_verilog_debug.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]