From 2e41138633257245ad6fa6feb1179a61f0a9ab2f Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Sun, 26 Jan 2020 17:56:22 -0700
Subject: [PATCH] use a micro benchmark for vpr quick-run

---
 openfpga/test_blif/riscv_core_lut6.blif       | 19187 ----------------
 openfpga/test_blif/s298.blif                  |    90 +
 .../{riscv_core.openfpga => s298.openfpga}    |     2 +-
 3 files changed, 91 insertions(+), 19188 deletions(-)
 delete mode 100644 openfpga/test_blif/riscv_core_lut6.blif
 create mode 100644 openfpga/test_blif/s298.blif
 rename openfpga/test_script/{riscv_core.openfpga => s298.openfpga} (74%)

diff --git a/openfpga/test_blif/riscv_core_lut6.blif b/openfpga/test_blif/riscv_core_lut6.blif
deleted file mode 100644
index a313bebc1..000000000
--- a/openfpga/test_blif/riscv_core_lut6.blif
+++ /dev/null
@@ -1,19187 +0,0 @@
-# Generated by Yosys 0.8+599 (git sha1 463f710, gcc 4.8.5 -fPIC -Os)
-
-.model riscv_core
-.inputs clock reset bus_read_data[0] bus_read_data[1] bus_read_data[2] bus_read_data[3] bus_read_data[4] bus_read_data[5] bus_read_data[6] bus_read_data[7] bus_read_data[8] bus_read_data[9] bus_read_data[10] bus_read_data[11] bus_read_data[12] bus_read_data[13] bus_read_data[14] bus_read_data[15] bus_read_data[16] bus_read_data[17] bus_read_data[18] bus_read_data[19] bus_read_data[20] bus_read_data[21] bus_read_data[22] bus_read_data[23] bus_read_data[24] bus_read_data[25] bus_read_data[26] bus_read_data[27] bus_read_data[28] bus_read_data[29] bus_read_data[30] bus_read_data[31] inst[0] inst[1] inst[2] inst[3] inst[4] inst[5] inst[6] inst[7] inst[8] inst[9] inst[10] inst[11] inst[12] inst[13] inst[14] inst[15] inst[16] inst[17] inst[18] inst[19] inst[20] inst[21] inst[22] inst[23] inst[24] inst[25] inst[26] inst[27] inst[28] inst[29] inst[30] inst[31] rs1_data[0] rs1_data[1] rs1_data[2] rs1_data[3] rs1_data[4] rs1_data[5] rs1_data[6] rs1_data[7] rs1_data[8] rs1_data[9] rs1_data[10] rs1_data[11] rs1_data[12] rs1_data[13] rs1_data[14] rs1_data[15] rs1_data[16] rs1_data[17] rs1_data[18] rs1_data[19] rs1_data[20] rs1_data[21] rs1_data[22] rs1_data[23] rs1_data[24] rs1_data[25] rs1_data[26] rs1_data[27] rs1_data[28] rs1_data[29] rs1_data[30] rs1_data[31] rs2_data[0] rs2_data[1] rs2_data[2] rs2_data[3] rs2_data[4] rs2_data[5] rs2_data[6] rs2_data[7] rs2_data[8] rs2_data[9] rs2_data[10] rs2_data[11] rs2_data[12] rs2_data[13] rs2_data[14] rs2_data[15] rs2_data[16] rs2_data[17] rs2_data[18] rs2_data[19] rs2_data[20] rs2_data[21] rs2_data[22] rs2_data[23] rs2_data[24] rs2_data[25] rs2_data[26] rs2_data[27] rs2_data[28] rs2_data[29] rs2_data[30] rs2_data[31]
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-.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][8] singlecycle_datapath.program_counter.value[8] re clock 2
-.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][9] singlecycle_datapath.program_counter.value[9] re clock 2
-.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][10] singlecycle_datapath.program_counter.value[10] re clock 2
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-.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][12] singlecycle_datapath.program_counter.value[12] re clock 2
-.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][13] singlecycle_datapath.program_counter.value[13] re clock 2
-.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][14] singlecycle_datapath.program_counter.value[14] re clock 2
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-.latch $abc$8517$techmap\singlecycle_datapath.program_counter.$0\value[31:0][31] singlecycle_datapath.program_counter.value[31] re clock 2
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diff --git a/openfpga/test_blif/s298.blif b/openfpga/test_blif/s298.blif
new file mode 100644
index 000000000..c588a6e0a
--- /dev/null
+++ b/openfpga/test_blif/s298.blif
@@ -0,0 +1,90 @@
+# Benchmark "s298" written by ABC on Tue Mar 12 09:40:31 2019
+.model s298
+.inputs clock G0 G1 G2
+.outputs G117 G132 G66 G118 G133 G67
+
+.latch        n21        G10 re      clock  0
+.latch        n26        G11 re      clock  0
+.latch        n31        G12 re      clock  0
+.latch        n36        G13 re      clock  0
+.latch        n41        G14 re      clock  0
+.latch        n46        G15 re      clock  0
+.latch        n51        G66 re      clock  0
+.latch        n55        G67 re      clock  0
+.latch        n59       G117 re      clock  0
+.latch        n63       G118 re      clock  0
+.latch        n67       G132 re      clock  0
+.latch        n71       G133 re      clock  0
+.latch        n75        G22 re      clock  0
+.latch        n80        G23 re      clock  0
+
+.names n56 n57 G10 n63
+0-0 1
+11- 1
+.names G15 G11 G13 G22 G14 G12 n56
+01---- 1
+0-0--- 1
+0--0-- 1
+0---1- 1
+0----1 1
+-11000 1
+.names G14 G13 G12 G118 G11 n57
+01--- 1
+100-0 1
+1-11- 1
+-1-1- 1
+.names n56 n59_1 G10 n67
+0-0 1
+11- 1
+.names G14 G13 G12 G132 G11 n59_1
+100-0 1
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+1-11- 1
+.names G0 G10 n21
+00 1
+.names G10 G11 G0 G12 G13 n26
+010-- 1
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+.names G12 G0 G11 G10 n31
+0011 1
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+00111 1
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+.names n65 G14 G0 n41
+000 1
+110 1
+.names G23 G10 G13 G11 G12 n65
+1---- 0
+-1100 0
+.names G0 n56 n46
+00 1
+.names n56 G66 G14 G13 G12 n51
+111-1 1
+11-1- 1
+1-01- 1
+.names n56 G13 G14 G11 G67 G12 n55
+1000-- 1
+10-1-0 1
+111-1- 1
+1-1-11 1
+.names n56 G13 G117 G14 G12 G11 n59
+10-0-- 1
+10--01 1
+1111-- 1
+1-111- 1
+.names n56 G14 G12 G13 G133 G11 n71
+1010-1 1
+111-1- 1
+11-11- 1
+.names G2 G22 G0 n75
+010 1
+100 1
+.names G1 G23 G0 n80
+010 1
+100 1
+.end
diff --git a/openfpga/test_script/riscv_core.openfpga b/openfpga/test_script/s298.openfpga
similarity index 74%
rename from openfpga/test_script/riscv_core.openfpga
rename to openfpga/test_script/s298.openfpga
index d2614df44..d9d1e15ca 100644
--- a/openfpga/test_script/riscv_core.openfpga
+++ b/openfpga/test_script/s298.openfpga
@@ -1,2 +1,2 @@
 # Run VPR for the RISC-V core
-vpr ./test_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ./test_blif/riscv_core_lut6.blif
+vpr ./test_arch/k6_frac_N10_frac_chain_depop50_mem32K_40nm.xml ./test_blif/s298.blif