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critical bug fixed in repacking. This is due to depop50% local routing where the same net may be mapped to two different pins in the same pb_graph_pin. Now we restrict the pin searching. But in long term, we should sync the pb_route results to post routing results

This commit is contained in:
tangxifan 2020-04-18 21:04:46 -06:00
parent f76a3090c4
commit 2e3a811f4f
3 changed files with 33 additions and 31 deletions
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7
openfpga/src/annotation/vpr_routing_annotation.cpp
View File

@ -36,9 +36,10 @@ void VprRoutingAnnotation::set_rr_node_net(const RRNodeId& rr_node,
/* Ensure that the node_id is in the list */ /* Ensure that the node_id is in the list */
VTR_ASSERT(size_t(rr_node) < rr_node_nets_.size()); VTR_ASSERT(size_t(rr_node) < rr_node_nets_.size());
/* Warn any override attempt */ /* Warn any override attempt */
if (ClusterNetId::INVALID() != rr_node_nets_[rr_node]) { if ( (ClusterNetId::INVALID() != rr_node_nets_[rr_node])
VTR_LOG_WARN("Override the net '%ld' for node '%ld' with in routing context annotation!\n", && (net_id != rr_node_nets_[rr_node])) {
size_t(net_id), size_t(rr_node)); VTR_LOG_WARN("Override the net '%ld' by net '%ld' for node '%ld' with in routing context annotation!\n",
size_t(rr_node_nets_[rr_node]), size_t(net_id), size_t(rr_node));
} }
rr_node_nets_[rr_node] = net_id; rr_node_nets_[rr_node] = net_id;

14
openfpga/src/repack/repack.cpp
View File

@ -117,15 +117,21 @@ int find_pb_route_remapped_source_pb_pin(const t_pb* pb,
for (int pin = 0; pin < pb->pb_graph_node->total_pb_pins; ++pin) { for (int pin = 0; pin < pb->pb_graph_node->total_pb_pins; ++pin) {
/* Bypass unused pins */ /* Bypass unused pins */
if ((0 == pb->pb_route.count(pin)) || (AtomNetId::INVALID() == pb->pb_route[pin].atom_net_id)) { if ((0 == pb->pb_route.count(pin)) || (AtomNetId::INVALID() == pb->pb_route.at(pin).atom_net_id)) {
continue; continue;
} }
/* Get the driver pb pin id, it must be valid */ /* Get the driver pb pin id, it must be valid */
if (atom_net_id != pb->pb_route[pin].atom_net_id) { if (atom_net_id != pb->pb_route.at(pin).atom_net_id) {
continue; continue;
} }
/* Only care the pin that shares the same parent_node as source_pb_pin */ /* Only care the pin has the same parent port as source_pb_pin
if (source_pb_pin->parent_node == pb->pb_route[pin].pb_graph_pin->parent_node) { * Due to that the source_pb_pin may be swapped during routing
* the pb_route is out-of-date
* TODO: should update pb_route by post routing results
* On the other side, the swapping can only happen between equivalent pins
* in a port. So the port must match here!
*/
if (source_pb_pin->port == pb->pb_route.at(pin).pb_graph_pin->port) {
pb_route_indices.push_back(pin); pb_route_indices.push_back(pin);
} }
} }

43
openfpga_flow/tasks/openfpga_shell/mcnc_big20/config/task.conf
View File

@ -21,31 +21,26 @@ openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k6_frac_N10
arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/arch/vpr_only_templates/k6_frac_N10_tileable_adder_register_scan_chain_depop50_40nm.xml
[BENCHMARKS] [BENCHMARKS]
# Pass #bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif
bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/alu4/alu4.blif #bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif
# Pass, but port does not match, i_15_ is dangling #bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif
bench1=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex2/apex2.blif #bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif
# Pass #bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif
bench2=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/apex4/apex4.blif #bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif
bench3=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/bigkey/bigkey.blif #bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif
# To be tested #bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif
bench4=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/clma/clma.blif #bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif
bench5=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/des/des.blif #bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif
bench6=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/diffeq/diffeq.blif #bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
bench7=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/dsip/dsip.blif #bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
bench8=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/elliptic/elliptic.blif #bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
bench9=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex1010/ex1010.blif #bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
bench10=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/ex5p/ex5p.blif
bench11=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/frisc/frisc.blif
bench12=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/misex3/misex3.blif
bench13=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/pdc/pdc.blif
# Pass
bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif bench14=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s298/s298.blif
bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif #bench15=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38417/s38417.blif
bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif #bench16=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/s38584/s38584.blif
bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif #bench17=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/seq/seq.blif
bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif #bench18=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/spla/spla.blif
bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif #bench19=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/mcnc_big20/tseng/tseng.blif
[SYNTHESIS_PARAM] [SYNTHESIS_PARAM]
# Benchmark alu4 # Benchmark alu4