From 2de6be44d6edaff8d5efd020057fc2dc7ad183d8 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Fri, 1 Oct 2021 18:27:42 -0700
Subject: [PATCH] [Engine] Fixed a critical bug which causes bitstream wrong
 for QuickLogic memory bank when fast configuration is enabled

---
 openfpga/src/utils/fabric_bitstream_utils.cpp | 25 +++++++++++++++++--
 1 file changed, 23 insertions(+), 2 deletions(-)

diff --git a/openfpga/src/utils/fabric_bitstream_utils.cpp b/openfpga/src/utils/fabric_bitstream_utils.cpp
index e09a99672..8d66f300f 100644
--- a/openfpga/src/utils/fabric_bitstream_utils.cpp
+++ b/openfpga/src/utils/fabric_bitstream_utils.cpp
@@ -235,13 +235,34 @@ MemoryBankFabricBitstream build_memory_bank_fabric_bitstream_by_address(const Fa
 MemoryBankFlattenFabricBitstream build_memory_bank_flatten_fabric_bitstream(const FabricBitstream& fabric_bitstream,
                                                                             const bool& fast_configuration,
                                                                             const bool& bit_value_to_skip) {
+  /* If fast configuration is not enabled, we need all the wl address even some of them have all-zero BLs */
+  if (!fast_configuration) {
+    vtr::vector<FabricBitRegionId, std::map<std::string, std::string>> fabric_bits_per_region;
+    fabric_bits_per_region.resize(fabric_bitstream.num_regions());
+    for (const FabricBitRegionId& region : fabric_bitstream.regions()) {
+      for (const FabricBitId& bit_id : fabric_bitstream.region_bits(region)) {
+        /* Create string for BL address */
+        std::string bl_addr_str(fabric_bitstream.bit_bl_address(bit_id).size(), bit_value_to_skip);
+
+        /* Create string for WL address */
+        std::string wl_addr_str;
+        for (const char& addr_bit : fabric_bitstream.bit_wl_address(bit_id)) {
+          wl_addr_str.push_back(addr_bit);
+        }
+
+        /* Deposit the config bit */
+        fabric_bits_per_region[region][wl_addr_str] = bl_addr_str;
+      }
+    }
+  }
+
   /* Build the bitstream by each region, here we use (WL, BL) pairs when storing bitstreams */
   vtr::vector<FabricBitRegionId, std::map<std::string, std::string>> fabric_bits_per_region;
   fabric_bits_per_region.resize(fabric_bitstream.num_regions());
   for (const FabricBitRegionId& region : fabric_bitstream.regions()) {
     for (const FabricBitId& bit_id : fabric_bitstream.region_bits(region)) {
-      /* Only when fast configuration is required, skip din because they should be pre-configured through programming reset/set */
-      if (fast_configuration && fabric_bitstream.bit_din(bit_id) == bit_value_to_skip) {
+      /* Skip din because they should be pre-configured through programming reset/set */
+      if (fabric_bitstream.bit_din(bit_id) == bit_value_to_skip) {
         continue;
       }
       /* Create string for BL address */