diff --git a/openfpga_flow/benchmarks/quicklogic_tests/routing_test/routing_test.act b/openfpga_flow/benchmarks/quicklogic_tests/routing_test/routing_test.act
deleted file mode 100755
index 19f52fdd9..000000000
--- a/openfpga_flow/benchmarks/quicklogic_tests/routing_test/routing_test.act
+++ /dev/null
@@ -1,10 +0,0 @@
-IN0 0.505000 0.204400
-IN1 0.491000 0.206000
-IN2 0.472000 0.204400
-clk 0.500000 2.000000
-OUT1 0.491000 0.206000
-OUT0 0.505000 0.204400
-OUT2 0.472000 0.204400
-n15 0.491000 0.101146
-n18 0.505000 0.103222
-n21 0.472000 0.096477
diff --git a/openfpga_flow/benchmarks/quicklogic_tests/routing_test/routing_test.v b/openfpga_flow/benchmarks/quicklogic_tests/routing_test/routing_test.v
deleted file mode 100644
index d9729c1c8..000000000
--- a/openfpga_flow/benchmarks/quicklogic_tests/routing_test/routing_test.v
+++ /dev/null
@@ -1,19 +0,0 @@
-
-module routing_test(IN0,IN1,IN2, clk, OUT0,OUT1,OUT2);
-
-input wire IN0,IN1,IN2,clk;
-
-output reg OUT0, OUT1, OUT2;
-
-always @(posedge clk)
-	begin
-
-		OUT0  <=  IN0;
-		OUT1  <=  IN1;
-		OUT2  <=  IN2;
-
-	end
-
-
-
-endmodule