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[Arch] Update openfpga architecture to include quicklogic cell sim

This commit is contained in:
tangxifan 2021-03-08 21:40:29 -07:00
parent 812d8c950e
commit 2daa770319
1 changed files with 2 additions and 2 deletions
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4
openfpga_flow/openfpga_arch/k4_frac_N8_reset_softadderSuperLUT_register_scan_chain_caravel_io_skywater130nm_fdhd_cc_openfpga.xml
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@ -206,9 +206,9 @@
<!-- A dummy model to include the adder_lut verilog code in testbench netlists <!-- A dummy model to include the adder_lut verilog code in testbench netlists
so that HDL simulation can be run when adder lut is used in users' implementations so that HDL simulation can be run when adder lut is used in users' implementations
--> -->
<!--circuit_model type="inv_buf" name="dummy1" prefix="dummy1" verilog_netlist="${OPENFPGA_PATH}/yosys/techlibs/quicklogic/openfpga_cells_sim.v"> <circuit_model type="inv_buf" name="dummy1" prefix="dummy1" verilog_netlist="${OPENFPGA_PATH}/yosys/techlibs/quicklogic/qlf_k4n8_cells_sim.v">
<design_technology type="cmos" topology="inverter" size="1"/> <design_technology type="cmos" topology="inverter" size="1"/>
</circuit_model--> </circuit_model>
</circuit_library> </circuit_library>
<configuration_protocol> <configuration_protocol>
<organization type="scan_chain" circuit_model_name="DFFRQ" num_regions="1"/> <organization type="scan_chain" circuit_model_name="DFFRQ" num_regions="1"/>