From 1b132fd667945ad3ca9d207072393380e585d082 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 22 Aug 2023 11:06:12 -0700 Subject: [PATCH 1/4] [test] add a new testcase to validate the support on different routing channel width on X and Y --- .../regression_test_scripts/basic_reg_test.sh | 2 + .../k4_series/k4n4_chandistr/config/task.conf | 38 + ...der_chain_mem1K_L124_ChanWidth0p8_40nm.xml | 723 ++++++++++++++++++ 3 files changed, 763 insertions(+) create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_chandistr/config/task.conf create mode 100644 openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124_ChanWidth0p8_40nm.xml diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index a96902f98..630de10ba 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -147,6 +147,8 @@ echo -e "Testing K4N4 with LUTRAM"; run-task basic_tests/k4_series/k4n4_lutram $@ echo -e "Testing K4N4 with multiple lengths of routing segments"; run-task basic_tests/k4_series/k4n4_L124 $@ +echo -e "Testing K4N4 with routing channel width distribution: x = 0.8, y = 1.0"; +run-task basic_tests/k4_series/k4n4_chandistr $@ echo -e "Testing K4N4 with 32-bit fracturable multiplier"; run-task basic_tests/k4_series/k4n4_frac_mult $@ echo -e "Testing K4N5 with pattern based local routing"; diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_chandistr/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_chandistr/config/task.conf new file mode 100644 index 000000000..99478308c --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_chandistr/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=4x4 +openfpga_vpr_route_chan_width=40 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124_ChanWidth0p8_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124_ChanWidth0p8_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124_ChanWidth0p8_40nm.xml new file mode 100644 index 000000000..35d56c98f --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124_ChanWidth0p8_40nm.xml @@ -0,0 +1,723 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + clb.clk + clb.cin + clb.O[3:0] clb.I[5:0] + clb.cout clb.O[7:4] clb.I[11:6] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 + 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 195e-12 + 195e-12 + 195e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 56cedf6c8b84a4c446e19103ba272b2b4e1f3163 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 22 Aug 2023 11:20:14 -0700 Subject: [PATCH 2/4] [test] added a new test case to validate the support on different wire segment distribution on X and Y --- ...n_mem1K_L124X_L12Y_40nm_frame_openfpga.xml | 277 +++++++ .../regression_test_scripts/basic_reg_test.sh | 2 + .../k4n4_chandistr_segdist/config/task.conf | 38 + ...ain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml | 733 ++++++++++++++++++ 4 files changed, 1050 insertions(+) create mode 100644 openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml create mode 100644 openfpga_flow/tasks/basic_tests/k4_series/k4n4_chandistr_segdist/config/task.conf create mode 100644 openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml diff --git a/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml new file mode 100644 index 000000000..f489b97f5 --- /dev/null +++ b/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml @@ -0,0 +1,277 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + 10e-12 + + + 10e-12 + + + + + + + + + + + + 10e-12 5e-12 + + + 10e-12 5e-12 + + + + + + + + + + + + + 10e-12 5e-12 5e-12 + + + 10e-12 5e-12 5e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/openfpga_flow/regression_test_scripts/basic_reg_test.sh b/openfpga_flow/regression_test_scripts/basic_reg_test.sh index 630de10ba..749765a33 100755 --- a/openfpga_flow/regression_test_scripts/basic_reg_test.sh +++ b/openfpga_flow/regression_test_scripts/basic_reg_test.sh @@ -149,6 +149,8 @@ echo -e "Testing K4N4 with multiple lengths of routing segments"; run-task basic_tests/k4_series/k4n4_L124 $@ echo -e "Testing K4N4 with routing channel width distribution: x = 0.8, y = 1.0"; run-task basic_tests/k4_series/k4n4_chandistr $@ +echo -e "Testing K4N4 with routing channel width distribution: x = 0.8, y = 1.0 and wire segment distribution: x=L124, Y=L12"; +run-task basic_tests/k4_series/k4n4_chandistr_segdist $@ echo -e "Testing K4N4 with 32-bit fracturable multiplier"; run-task basic_tests/k4_series/k4n4_frac_mult $@ echo -e "Testing K4N5 with pattern based local routing"; diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_chandistr_segdist/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_chandistr_segdist/config/task.conf new file mode 100644 index 000000000..91eda2fd4 --- /dev/null +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_chandistr_segdist/config/task.conf @@ -0,0 +1,38 @@ +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# Configuration file for running experiments +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = +# timeout_each_job : FPGA Task script splits fpga flow into multiple jobs +# Each job execute fpga_flow script on combination of architecture & benchmark +# timeout_each_job is timeout for each job +# = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = + +[GENERAL] +run_engine=openfpga_shell +power_tech_file = ${PATH:OPENFPGA_PATH}/openfpga_flow/tech/PTM_45nm/45nm.xml +power_analysis = true +spice_output=false +verilog_output=true +timeout_each_job = 20*60 +fpga_flow=vpr_blif + +[OpenFPGA_SHELL] +openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scripts/fix_device_route_chan_width_example_script.openfpga +openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml +openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml +openfpga_vpr_device_layout=4x4 +openfpga_vpr_route_chan_width=40 + +[ARCHITECTURES] +arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml + +[BENCHMARKS] +bench0=${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.blif + +[SYNTHESIS_PARAM] +bench0_top = and2 +bench0_act = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.act +bench0_verilog = ${PATH:OPENFPGA_PATH}/openfpga_flow/benchmarks/micro_benchmark/and2/and2.v + +[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH] +end_flow_with_test= +vpr_fpga_verilog_formal_verification_top_netlist= diff --git a/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml new file mode 100644 index 000000000..095a82096 --- /dev/null +++ b/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml @@ -0,0 +1,733 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + io.outpad io.inpad + + + + + + + + + + + + + + + + + + + + clb.clk + clb.cin + clb.O[3:0] clb.I[5:0] + clb.cout clb.O[7:4] clb.I[11:6] + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 1 1 + 1 + + + + 1 1 1 + 1 1 + + + + 1 1 1 1 1 + 1 1 1 1 + + + + 1 1 + 1 + + + + 1 1 1 + 1 1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 235e-12 + 235e-12 + 235e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 195e-12 + 195e-12 + 195e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 261e-12 + 261e-12 + 261e-12 + 261e-12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + From 1ee46523233438eb0c2f98d728abc46ed63388f6 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 22 Aug 2023 15:15:55 -0700 Subject: [PATCH 3/4] [lib] update vtr which supports different x y axis in segments --- vtr-verilog-to-routing | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vtr-verilog-to-routing b/vtr-verilog-to-routing index 62fa48399..ec634df07 160000 --- a/vtr-verilog-to-routing +++ b/vtr-verilog-to-routing @@ -1 +1 @@ -Subproject commit 62fa48399eabb8788844ad852fca6cdec800accf +Subproject commit ec634df07a5be186a0e7b66f2789c4daf2e4b44c From db0bb291c2c6b11909ccc7da4461bd178897c664 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Tue, 22 Aug 2023 15:22:48 -0700 Subject: [PATCH 4/4] [test] update settings --- .../k4_series/k4n4_chandistr_segdist/config/task.conf | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_chandistr_segdist/config/task.conf b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_chandistr_segdist/config/task.conf index 91eda2fd4..e948a73b5 100644 --- a/openfpga_flow/tasks/basic_tests/k4_series/k4n4_chandistr_segdist/config/task.conf +++ b/openfpga_flow/tasks/basic_tests/k4_series/k4n4_chandistr_segdist/config/task.conf @@ -20,7 +20,7 @@ openfpga_shell_template=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_shell_scrip openfpga_arch_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_arch/k4_frac_N4_adder_chain_mem1K_L124X_L12Y_40nm_frame_openfpga.xml openfpga_sim_setting_file=${PATH:OPENFPGA_PATH}/openfpga_flow/openfpga_simulation_settings/auto_sim_openfpga.xml openfpga_vpr_device_layout=4x4 -openfpga_vpr_route_chan_width=40 +openfpga_vpr_route_chan_width=60 [ARCHITECTURES] arch0=${PATH:OPENFPGA_PATH}/openfpga_flow/vpr_arch/k4_frac_N4_tileable_adder_chain_mem1K_L124X_L12Y_ChanWidth0p8_40nm.xml